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18 | Keysight | M9391A PXIe Vector Signal Analyzer 1 MHz to 3 or 6 GHz - Specifications Guide
Technical Specifications and Characteristics
Measurement speed
46
IQ data capture
47
Nominal
Large block (50 MSamples) 1.5 s Transferred in 100 kSa or 1 MSa blocks
Small block (100 captures, 100 ksamples each) 292 ms Transferred in 10 kSa blocks
Adjust level, freq (10 ksamples) 1.7 ms Transferred in 10 kSa blocks
Power measurements
48
Channel power settings & filter bandwidth Acquisition Time Averages Nominal
3.84 MHz 400 µs None 1.8 ms
10 7.6 ms
100 µs None 1.3 ms
10 4.1 ms
50 µs None 1.3 ms
10 3.4 ms
30 kHz 100 µs None 3.9 ms
10 30.4 ms
Format specific measurement data
GSM 49, 50
Parameters Nominal
Global phase error 0.9, 1.8, 1.9, 2.0, 2.1, 2.2 GHz 0.17 º
ORFS dynamic range 200 kHz offset −36 dBc
250 kHz offset −41 dBc
400 kHz offset −69 dBc
600 kHz offset −73 dBc
800 kHz offset −77 dBc
1200 kHz offset −80 dBc
1800 kHz offset −78 dBc
EDGE
49, 50
Parameters Nominal
Residual EVM 0.9, 1.8, 1.9, 2.0, 2.1, 2.2 GHz 0.23% rms
ORFS dynamic range 200 kHz offset −37 dBc
250 kHz offset −42 dBc
400 kHz offset −69 dBc
600 kHz offset −73 dBc
800 kHz offset −77 dBc
1200 kHz offset −80 dBc
1800 kHz offset −77 dBc
46. EVM, ACPR and servo loop test times for the RF power amplifier test, reference solution are included in the solution brochure 5991-4104EN.
47. Capture block, transfer to host memory, 160 MHz BW, excludes frequency transitions below 400 MHz, with M9037A embedded controller
(2-link configuration: 1 x 8 [factory default]).
48. Transfer to host memory, 160 MHz IF bandwidth filter, excludes frequency transitions below 400 MHz, with M9037A embedded controller
(2-link configuration: 1 x 8 [factory default]).
49. Synthesizer PLL mode set to PLL mode best wide offset.
50. Expected input level 0 dBm, input signal (total power) 0 dBm, mixer level 10 dB, conversion type: Auto, PeakToAverage set per signal peak to average.