Kenwood TK-80, Руководство по обслуживанию

Страница: 12 / 125

TK-80
11
2-3. LO2 (PLL loop)
The part oscillated by X502 and Q517 is output to LO1
cancel loop after passing through the Q518 buffer and input
into mixer IC505. The other part is output from CN502 as
LO2.
2-4. CAR
A digital signal is generated near 695kHz at IC501, and the
analog signal converted by the CP502, CP503 ladder resis-
tors and Q522 D/A converter are mixed with the 10MHz gen-
erated from the chop output of IC501 at IC506. This is then
output as 10.695MHz through the band-pass filter and the
amplifier.
During receiving AM mode, the DDS oscillation is
stopped. In FSK mode, the internal register of IC501 is
switched for direct FSK modulation by the external RTK sig-
nal during selective call mode code transmission by the ABSL
signal from the CPU.
2-5. DDS circuit configuration
The DDS IC has been developed with standard cells to
implement a high-speed circuit and large-capacity ROM at
low cost.
Q526
2SC2714(Y)
Q525
2SC2714(Y)
Q514
2SC2712(GR)
20MHz
Q527
2SC2996(Y)
Q529
2SC2712(Y)
Q528
2SC2996(Y)
Q536
2SC2714(Y)
Q507
2SC2714(Y)
Rin
1/40 PD
1/N
15
IC502
MB86001PF
SO-2
OSC
OPTION
DO2
9
Fin
6
Q508~510
2SC3722K(R)
A. LPF
BPF
LPF
LPF
LPF
BPF DDS1
LPF
VCO2
VCO3
VCO1
Q511
2SC2714(Y)
Q512
2SC2712(Y)
Q515
2SC2712(Y)
Q523
2SC2712(Y)
Q516
2SC2712(Y)
Q513
2SC2714(Y)
19.5~
49.5MHz
BPF
53.545~
54.045MHz
LO1
: 73.145~
103.045MHz
3.4dBm
LO2
: 62.35MHz
2.5dBm
CAR
: 10.695MHz
–1.2dBm
IC503
NJM2594V
+
+
+
+
–
–
+
–
Q531,533,535
2SK508NV(K52)
PLL
IC500
F71022Z
CF500
Q522
2SC2712(GR)
DDS2
IC501
F71022Z
∆
IC504
NJM2594V
IC506
NJM2594V
IC505
UPC1686G
8.305~
8.805MHz
Q519
2SC2714(Y)
Q518
2SC2714(Y)
Q520
2SC2714(Y)
Q524
2SC2714(Y)
Q521
2SC2714(Y)
OSC
Q517
2SC2714(Y)
62.35MHz
1.195~
1.695MHz
CHOP
10MHz
10.695MHz
N=39~99
VCO1: 73.145~83.544MHz
VCO2: 83.545~94.544MHz
VCO3: 94.545~103.045MHz
■
IC configuration
IC configuration is as follows:
• There are two 28 bit registers for setting frequency data,
one 28 bit frequency shift register for addition to the fre-
quency registers, a 23 bit parallel signal input section for
frequency modulation with parallel signals, and a data en-
try and selection section.
• There is a frequency-modulation section comprising 28 bit
adders for adding frequency data and frequency modula-
tion data, a phase data operation section that adds data
from the frequency modulation section and 28 bit phase
data register, and a SIN-ROM that converts phase data to
sine waves.
■ Frequency/shift data setting
Using serial signals synchronized with clock pulses, 30
bits (2 bits that specify the destination for which data is set,
and 28 bits of frequency data) are set in the three internal
registers.
■
Frequency register selection
The data set in the two frequency registers is selected by
the SLAB input of the DDS IC. This pin handles the ABSL
signal for IC501, and the CASL signal for IC500. This function
eliminates the need for the TK-80 to set frequency data for
each transmission/reception with the microprocessor.
Fig. 2 PLL block diagram and frequency configuration
CIRCUIT DESCRIPTION