TK-385
8
5. Frequency Synthesizer Unit
5-1. Frequency synthesizer
The frequency synthesizer consists of the VCXO (X1), VCO
(A1), PLL IC(IC14) and buffer amplifiers.
The VCXO generates 16.8MHz. The frequency stability is
1.5ppm within the temperature range of -30 to +60˚C. The
frequency tuning and modulation of the VCXO are done to
apply a voltage to pin 1 of the VCXO. The output of the VCXO
is applied to pin 8 of the PLL IC.
The TK-385’s VCO consists of 2VCO and covers a dual range
of the 405.15~425.15MHz and the 450~470MHz. The VCO
generates 405.15~425.15MHz for providing to the first local signal
in receive. In TX, the pin 3 of the VCO goes low and the VCO
generates 450~470MHz.
The output of the VCO is amplified by the buffer amplifier
(Q16) and routed to the pin 5 of the PLL IC. Also the output of
the VCO is amplified by the buffer amplifier (Q18) and routed
to the next stage according to T/R switch (D9, D23).
The PLL IC consists of a prescaler, fractional divider,
reference divider, phase comparator, charge pump. This PLL
IC is fractional-N type synthesizer and performs in the 40.50
or 60kHz reference signal which is eighth of the channel step
(6.25kHz). The input signal from the pins 5 and 8 of the PLL IC
is divided down to the 50kHz and compared at phase
comparator. The pulsed output signal of the phase comparator
is applied to the charge pump and transformed into DC signal
in the loop filter (LPF). The DC signal is applied to the pin 1 of
the VCO and locked to keep the VCO frequency constant.
PLL data is output from DT (pin 75). CP (pin 19) and EP
(pin 47) of the microprocessor (IC19). The data are input to
the PLL IC when the channel is changed or when transmission
is changed to reception and vice versa.
Fig. 8 PLL block diagram
T/R
(TX : Low)
T/R
A1
VCO
CV
5
IC14
PLL
8
BUFF
BUFF
LPF
DT,CP,EP
CPU
UL
IC19
VCXO
IC1
FC
BAL
Q18
SW
D9
To
drive
amp
Q16
X1
To mixer
SW
MB
D23
18
CIRCUIT DESCRIPTION
The output signal from the summing amplifier passes
through the D/A converter (IC8) again and goes to the VCO
modulation input.
The other output signal from the summing amplifier passes
through the D/A converter (IC8) again for the BAL adjustment,
and the buffer amplifier (IC1 (2/2)), and goes to the VCXO
modulation input.
4-2. Drive and Final amplifier
The signal from the T/R switch (D9 is on) is amplified by the
pre-drive (Q18) and drive amplifier (Q20) to 50mW.
The output of the drive amplifier is amplified by the RF power
amplifier (IC100) to 4.0W (1W when the power is low). The RF
power amplifier consists of two stages MOS FET transistor.
The output of the RF power amplifier is then passed through
the harmonic filter (LPF) and antenna switch (D12, D401 is
on) and applied to the antenna terminal.
Fig. 6 Microphone amplifier
Fig. 7 Drive and final amplifier and APC circuit
12
HPF
LPF
HPF
IDC
PRE
EMP
ALC
COMP
SW
LIMIT
SW
MIC
Q300
D8
LPF
IC25 (1/2)
MIC
EXT.
MIC
Q301
IC13
15
16
18
19
Q13
MUTE
DTMF
9
8
6
D/A
D/A
IC8
IC8
IC1
I5
O5
I1
O1
D/A
IC8
I2
O2
LSD
DI9
IC7 (1/2)
SUM
AMP
BUFF
AMP
VCXO
VCO
A1
X1
MIC
MUTE
Q17
PTT
MSW
From
T/R SW
(D9)
Pre-DRIVE
AMP
DRIVE
AMP
RF
POWER AMP
LPF
ANT
SW
D12,D401
ANT
VGG
Q18
Q20
IC100
VDD
R245
R247
R249
+B
IC23
(1/2)
IC23
(2/2)
REF
VOL
(IC8)
4-3. APC circuit
The APC circuit always monitors the current flowing through
the RF power amplifier (IC100) and keeps a constant current.
The voltage drop at R245, R247 and R249 is caused by the
current flowing through the RF power amplifier and this voltage
is applied to the differential amplifier (IC23 1/2).
IC23(2/2) compares the output voltage of IC23(1/2) with
the reference voltage from IC8, and the output of IC23(2/2)
controls the VGG of the RF power amplifier to make the both
voltages to same voltage.
The change of power high/low is carried out by the change
of the reference voltage. Q22,23 and 25 are turned on in
transmit and the APC circuit is active.
