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4-2
Interrupts and I/O Address Mapping
KPCI-PIO24 User’s Manual
Interrupts
Two externally accessible inputs allow for flexible interrupt configuration: INT_EN (external
interrupt enable, active low) and INT_REQ (external interrupt request, edge triggered). The
interrupt pins on the I/O connector are identified in Figure 3-1.
The external interrupt request line can be set in software to trigger on either the positive (rising)
edge or the negative (falling) edge of the signal; positive edge triggering is the default upon
power-up or reset. Also, when one or more ports are configured as inputs, the interrupt request
line can be simultaneously programmed to latch incoming data on this edge. Refer to the KPCI-
PIO24 software manual for more information on setting and configuration of the
external interrupts.
The PCI bus shares a single interrupt line for all cards, INTA, which interrupts the host computer
every time a transfer is occurring. This interrupt is internal to the PCI bus. It must not be confused
with the external interrupt line, INT_REQ, even though INT_REQ and INTA are linked
by software.
I/O address mapping
NOTE
A typical user of the KPCI-PIO24 board does not need to read this
section. Register level programming of your board is neither practical
nor necessary for most users. Register level interfacing with the PCI
bus is more complex than with the ISA bus. PCI board addresses are
mapped automatically in general memory, whereas ISA board
addresses are assigned by the user to memory reserved for I/O.
The DriverLINX driver shipped with your board provides a user-friendly Application
Programming Interface (API) that supports Visual C++, Visual Basic, and Delphi programming
languages under Windows 95/98 and Windows NT 4.0. You are strongly encouraged to use the
capabilities of DriverLINX and ignore the rest of the information in this chapter.
However, there are circumstances in which advanced uses may desire or need to bypass
DriverLINX entirely and write their own drivers. Alternatively, advanced users may wish to use
DriverLINX with programming languages other than Visual C++, Visual Basic, or Delphi.
Ways to accomplish these tasks are referenced under “Setting control and data registers.” The
remainder of the chapter summarizes general and relative register addresses and
register assignments.
General memory assignments
The PCI specification allows each card to be assigned up to five distinct memory regions. The
first region, BADDR 0, is mandatory per the PCI specification, as published by the PCI Special
Interest Group (PCISIG). BADDR 0 contains all information needed to identify a PCI device.
BADDR 0 also contains specific operation registers for the AMCC S5933 bus controller. These
operation registers hold all control and status information, as well as FIFOs, for PCI-initiated bus
mastering. The other four memory regions are BADDR1, BADDR2, BADDR3, and BADDR4.
These regions are left for custom designs and operate only in the target mode, also called
passthrough operation (memory access through the CPU). High speed data transfer via bus
mastering is unnecessary for the simple digital I/O of the KPCI-PIO24 board.
Содержание KPCI-PIO24
Страница 12: ...1 Overview...
Страница 14: ...2 General Description...
Страница 18: ...3 Installation...
Страница 29: ...4 Interrupts and I O Address Mapping...
Страница 35: ...5 Troubleshooting...
Страница 38: ...5 4 Troubleshooting KPCI PIO24 User s Manual Figure 5 1 Problem isolation flowchart...
Страница 56: ...A Specifications...
Страница 58: ...B Glossary...