JYTEK USB-61210, Руководство пользователя

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30 Operation & Calibration
As shown, after the operation starts, the first scan of data is immedi -
ately acquired when the trigger signal is deasserted and paused when
the trigger signal is asserted.
The remaining A/D conversions are not performed until the trigger sig
-
nal is deasserted again. The process repeats until the specified amount
of data is acquired.
Figure 3-13: Gated Trigger
3.1.5 Programmable Function I/O
The USB-61210 supports powerful programmable I/O function provided
by an FPGA chip, configurable as LVTTL DI/DO, 32-bit timer/counters,
and PWM output. These signals are single-ended and 5 V LVTTL-compli -
ant.
LVTTL DI/DO
Programmable function I/O can be used as static LVTTL-compliant 8-CH
digital input and 4-CH digital output. You can read/write these I/O lines
by software polling, with sample and update rate fully controlled by
software timing.
Pin# Pin#
IGND 20 40 IGND
GPI0 19 39 GPO0
GPI1 18 38 GPO1
GPI2 17 37 GPO2
GPI3 16 36 GPO3
Time
Ɣ Operation initiates
Trigger
(Active High)
Data
Ɣ Acquisition begins
Ɣ Acquisition stops
Ɣ Acquisition begins Ɣ Acquisition stops
Ɣ Acquisition begins