1-26 (No.XA001)
SECTION 4
Description of major ICs
4.1
74LVC373APW-X (IC512, IC513) : Octal D-type transparet latch
• Pin Layout
• Pin function
• Truth table
H=HIGH Voltage Levelh=HIGH Voltage level one setup time prior to the HIGH-to-LOW LE transitionL=LOW Vlotage Levell=LOW
Voltage level one setup time prior to the HIGH-to-LOW LE transitionX=Don't careZ=High Impedance OFF-state
• Block Diagram
(TOP VIEW)
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Symbol
Description
D0-D7
Data Inputs
LE
Latch enable Input (active-high)
OE
Output enable Input (active-low)
Q0-Q7
Data outputs
GND
Connect to ground
Vcc
Power supply
Operating modes
Inputs
Internal latches
Outputs
OE
LE
Dn
Q0 to Q7
Enable and read register
(trasparant mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
L
L
L
L
l
h
L
H
H
H
Latch register and
disable outputs
H
H
L
L
l
h
L
H
Z
Z
Q
LE
D
D0
3
2
Q0
11
1
LE
OE
Q
LE
D
D1
4
5
Q1
Q
LE
D
D2
7
6
Q2
Q
LE
D
D3
8
9
Q3
Q
LE
D
D4
13
12
Q4
Q
LE
D
D5
14
15
Q5
Q
LE
D
D6
17
16
Q6
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
D
D7
18
19
Q7
Содержание XV-C5SL
Страница 59: ...XV C5SL 2 7 MEMO 2 15 ...