JVC RX-DV5RSL, Руководство по обслуживанию

Страница: 37 / 105

1-37
RX-DV5RSL
W986432DH-7
DQ19~20
VssQ
DQ21~22
VccQ
DQ23
Vcc
Vss
DQ24
VssQ
DQ25~26
VccQ
DQ27~28
VssQ
DQ29~30
VccQ
DQ31
NC
Vss
DQM3
A3~A9
CKE
CLK
NC
DQM1
Vss
NC
DQ8
VccQ
DQ9~10
VssQ
DQ11~12
VccQ
DQ13~14
VssQ
DQ15
Vss
Pin No.
I/O
I/O
I/O
-
I/O
-
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
-
-
I/O
-
-
I
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
Symbol
36~37
38
39~40
41
42
43
44
45
46
47~48
49
50~51
52
53~54
55
56
57
58
59
60~66
67
68
69~70
71
72
73
74
75
76~77
78
79~80
81
82~83
84
85
86
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Ground for input buffers and logic circuit inside DRAM.
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
No connection
Ground for input buffers and logic circuit inside DRAM.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Multiplexed pins for row and column address. Row address: Ao-A10.
Column address:A0-A7.A10 is sampled during a recharge command to
determine if all banks are to be recharged or bank selected by BS0, BS1.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down rising edge of clock.
System clock used to sample inputs on the rising edge of clock.
No connection
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Ground for input buffers and logic circuit inside DRAM.
No connection
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Ground for input buffers and logic circuit inside DRAM.
Function