5
4
3
2
1
A
B
C
D
E
F
G
2-55
2-56
*4
VIDEO BLOCK DIAGRAM (2/2)
TO
PHYXTP
A
16
20
IC8001
156
82
PHYTPB
PHYTP
A
226
286
PHYXTPB
185
109
108
AIMCK
AIBCK
AILRCK
TPB-
TP
A-
TPB+
TP
A+
AID
A
T
AO
D
A
T
AILRCK
AIBCK
246
AID
A
T
1
AO
D
A
T
0
AIMCK
AID
A
T
0
248
112
OSC27I
CPUWAIT
XCPURW
XCPUDSTB1
XCPUDSTB0
CPUALE
BRSO0
BRSO3
142
DALE
DV_WATT
66
DRWSEL
213
143
212
150
67
DV_RST
ADDT15
ADDTO0
AD0
64
AD15
XRST
CLK27
38
191
255
119
39
INV
INH
BRSI3
BRSI0
117
YSI0
YSI3
43
122
OUTH
OUTV
MAIN
0
1
257
193
194
258
YSO3
YSO0
242
Sync Detect
IEE1394
LINK
(ISO/
ASYNC
FIFO)
D-RAM I/F
HOST
CPU
I/F
(DECK_DSP)
CONV)
(CLOCK
RAM
CONV)
(CLOCK
RAM
CONV)
RAM
(CLOCK
CORE)
RISC
RAM
PROGRAM
AUDIO
(WORK
ID Protect
De-formatting)
(CLOCK
CONV)
RAM
SPA
HSP
HID
TRKREF
FRREF
98
101
243
240
TSR
FRP
RAM
(SUB/AUX)
IC3001(DVMAIN)
RAM)
(VBID DET
VIDEO I/F
(ENC/DET)
RAM)
VLD WORK
COMPRESS
(DCT,VLC
OUTER ECC
FORMATTER
(Formatting
INNER ECC
(ENC/DEC)
PWMAUDIO
RECDATA
RECCTL
RECCLK
173
174
100
182
AUDIO_CS
S_SHUT
PD_L
DV IN/OUT
TPB+
TPB-
TPA-
DV
TPA+
TO IC3001
AIDAT
AODAT
AIBCK
AILRCK
AIMCK
AUDIO
TO
AUDIO
TO
SPA
RECCTL
RECDATA
RECCLK
FSPLLCTL
DAAOUT0
DAAOUT1
DISCRI
OSC27I
OSC27O
PWM27O
11
237
106
IC3005
AMP+
AMP-
AMPO
4
1
2
A0~A19
DQ0~DQ15
IC8003
(16M_FLASH
RAM)
9
45
25
29
DSC R/D_DATA
DSC R/D_ADRESS
39
108
7
20
HDDSC
CLKDSC
DSYO7
DSCO0
VDDSC
FLDDSC
DSC_WKUP
DSC_CS
FLSH_RST
DSC_CLK
DSC_DT_OUT
DSC_DT_IN
USBDOWN
DSC_RST
MXDT_OUT
CAPT_REQ
DSC_STS
DSYO0
DSCO7
DSCIO0
DSCIO7
DSYIO7
CN111
DSYIO0
CN8001
176
246
244
188
247
191
190
237
235
172
249
199
212
219
157
125
206
184
135
205
182
127
138
204
221
IC8004
TO
IC8003-12PIN
1
3
YIO0
YIO7
CIO0
CIO7
YIN0
YIN7
CIN0
CIN7
CLKIN1
HDIN
VDIN
FID
MXI
CLKIN2
GIO0
GIO18
SCLK1
SDI1
26
28
11
12
FLSH_CE
FLSH_OE
FLSH_WE
RESET
SDO1
GIO13
RESET
GIO16
GIO7
GIO11
USB_DN
USB_DP
FROM
RAS
WE
CS
CAS
CKE
CLK
A0
2
DQ0
16
159
51
2
3
49
30
177
201
160
200
193
180
SDRAM_DATA
SDRAM_ADRESS
IC8002
SDRAM
CXO
X8002
48MHz
2
MMC_CLK
5
7
9
174
173
250
117
SDI3
SCK3
SDO3
GIO20
ARM_D15
ARM_D0
ARM_A19
ARM_A0
EM_CS_O
EM_OE
EM_WE
M48XI
M48XO
SDR_DQ0
SDR_A0
SDR_CKE
SDR_CLK
SDR_CS
SDR_CAS
SDR_DQMLH
SDR_RAS
SDR_WE
SDR_DQMLL
DSC
TO TG
11
85
9
D8001
R8068
R3034
FSPLLCTL
R3010
R3009
C3024
M_VCOCTL
L3007
C3023
R3011
D3001
23
104
105
24
(PRE/REC)
48
AGC_BUFF_OUT
10
REC_GAIN
57
PB_MONI
12
44
7
MONI_CHG
R_CTL
REC_DATA
9
REC_CLK
Y1
19
X2
25
X1
20
HID3
40
42
41
HID1
REC_H
PB_H
38
Y2
24
IC3501
2
4
IC3502
HEAD
2
1F
7
3
6
2S
1S
2F
116
b
a
c
TO
CAMERA DSP
TO
CAMERA DSP
d
TO
CPU
TO
CAMERA DSP
TO
CAMERA DSP
CDDSTB
CDWE
CLK27BO
CPU
HID1
AO5
FSPLLCTL
RECCADJ
ATF_GAIN
4
18
19
5
AO1
AO2
AO6
IC3002
(DVMAIN)
VIPD_OUT
VIFD_OUT
17
DI
CLK
16
ADVIN0
AGC_OUT
168
J501
AU_DATA
AU_CLK
TO
SD/MMC
SOCKET
CN103
MMC_DATA
M32_MMC
MMC_CMD
IC1001-6PIN
146
SDR_DQ31
C8026
239
R8022
R8032
TO
CPU
TO
J502
TO
CAMERA DSP
CLK27B
64M
DQMO
DQM1
A10
DQ31
19
17
16
20
18
71
67
68
25
24
56
151
129
122
ENV_OUT
RECCADJ
GC_OUT
MONI_CHG
REC_DATA
REC_CTL
REC_CLK
HID1
RECH
PBH
HID3
ENV_OUT
RECCADJ
GC_OUT
ATF_GAIN
ATF_GAIN
MONI_CHG
REC_DATA
REC_CTL
REC_CLK
HID1
RECH
PBH
HID3
TO
CPU
TO
JIG CONN
(CN105)
3
5
6
4
25
7
33
8
11
14
22
23
38
36
35
37
16
34
8
33
30
27
19
18
CN110
CN401
60
PREMDA
0
5
CN402
SDR_A10
TO CPU
*1 WITH ANALOG INPUT MODEL
*2 WITHOUT ANALOG INPUT MODEL
*3 WITH EDIT MODEL
*4 WITH DSC MODEL
Содержание GR-D30EK
Страница 54: ...2 43 2 44 1 2 3 4 A B C PREMDA CIRCUIT BOARD 05 PREMDA YB 10405 01 01 FOIL SIDE B ...
Страница 130: ...2 43 2 44 1 2 3 4 A B C PREMDA CIRCUIT BOARD 05 PREMDA YB 10405 01 01 FOIL SIDE B ...
Страница 224: ...2 43 2 44 1 2 3 4 A B C PREMDA CIRCUIT BOARD 05 PREMDA YB 10405 01 01 FOIL SIDE B ...