NJU39612
T [mNm]
1
T [mNm]
2
max
T
nom
T
min
T
I [mA]
1
I [mA]
2
I
CS A0 Data Transfer
0 0 D7 —> Sign1, (D6—D0) —> (Q61—Q01)
0 1 D7 —> Sign2, (D6—D0) —> (Q62—Q02)
1 X No Transfer
Current Direction, Sign
1
& Sign
2
These bits are transferred from D
7
when writing in the respective DA register. A
0
must be set according to the data
transfer table in figure 7.
DA
1
and DA
2
These are the two outputs of DAC1 and DAC2. Input to the DACs are internal data bus (Q
61
… Q
01
) and (Q
62
… Q
02
).
Reference Voltage V
Ref
V
Ref
is the analog input for the two DACs. Special care in layout, gives a very low voltage drop from pin to resistor.
Any V
Ref
between 0.0 V and V
DD
can be applied, but output might be non-linear above 3.0 V.
Power-on Reset
This function automatically resets all internal flip flops at power-on. This results in V
SS
voltage at both DAC outputs
and all digital outputs.
Reset
If Reset is not used, leave it disconnected. Reset can be used to measure leakage currents from V
DD
.
Figure 7. Table showing how data is transfered inside NJU39612.
Figure 6b. An example of acces-
sible positions with a given torque
deviation/fullstep. Note that 1:st
µ
step sets highest resolution. Data
points are exaggerated for illustra-
tion purpose.
TNom = code 127.
Figure 6a. Assuming that torque is
proportional to the current in resp.
winding it is possible to draw figure
8b.
