NJU39612
Figure 2. Pin configuration
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
D6
WR
D7
D4
D0
CS
A0
NC
V
ref
D5
DA
1
Sign
1
VDD
Reset
DA
2
Sign
2
V
ss
D3
D2
D1
19
20
NJU39612E2
■
PIN CONFIGURATION
■
PIN DESCRIPTION
Refer to figure 2.
EMP
Symbol
Description
1
V
Ref
Voltage reference supply pin, 2.5 V nominal (3.0 V maximum)
2
DA
1
Digital-to-Analog 1, voltage output. Output between 0.0 V and V
ref
- 1 LSB.
3
Sign
1
Sign 1, TTL/CMOS level. To be connected directly to NJM377x phase input. Databit D7 is transfered non
inverted from NJU39612 data input.
4
V
DD
Voltage Drain-Drain, logic supply voltage. No5 V.
5
WR
Write, TTL/CMOS level, input for writing to internal registers. Data is clocked into flip flops on positive
edge.
6
D7
Data 7, TTL/CMOS level, input to set data bit 7 in data word.
7
D6
Data 6, TTL/CMOS level, input to set data bit 6 in data word.
8
D5
Data 5, TTL/CMOS level, input to set data bit 5 in data word.
9
D4
Data 4, TTL/CMOS level, input to set data bit 4 in data word.
10
D3
Data 3, TTL/CMOS level, input to set data bit 3 in data word.
11
D2
Data 2, TTL/CMOS level, input to set data bit 2 in data word.
12
D1
Data 1, TTL/CMOS level, input to set data bit 1 in data word.
13
D0
Data 0, TTL/CMOS level, input to set data bit 0 in data word.
14
A0
Address 0, TTL/CMOS level, input to select data transfer, A0 selects between cannel 1 (A0 = LOW) and
channel 2 (A0 = HIGH).
15
NC
Not connected
16
CS
Chip Select, TTL/CMOS level, input to select chip and activate data transfer from data inputs. LOW level
= chip is selected.
17
V
SS
Voltage Source-Source. Ground pin, 0 V reference for all signals and measurements unless otherwise
noted.
18
Sign
2
Sign 2. TTL/CMOS level. To be connected directly to NJM377x phase input. Data bit D7 is transfered
non-inverted from NJU39612 data input.
19
DA
2
Digital-to-Analog 2, voltage output. Output between 0.0 V and V
ref
- 1 LSB.
20
Reset
Reset, digital input resetting internal registers. HIGH level = Reset, V
Res
≥
3.5 V = HIGH level. Pulled low
internally.
