26
PAC will translate the original issued address via a translation table that is maintained on the
main memory. The option allows the selection of an aperture size of 32MB, 64MB.
Please refer to section 3-6-2
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
3-6-1 DRAM Timing Setting
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
DRAM Timing Setting
Item Help
Auto Configuration Standard
RAS Active Time 7T
RAS Precharge Time 2T
RAS to CAS Delay 2T
Write Recovery Time 2T
CAS Latency Setting 2.5T
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS Active Time
Select the number of SCLKs for an access cycle. The settings are: Auto (Default), 6T, 7T, 5T,
4T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 7T, 6T and 5T.
RAS to CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T.
CAS Latency Setting
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto (Default) 2T and 3T.
3-6-2 AGP Function Settings
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
AGP Function Settings
