JETWAY 615TCFR1C, Руководство пользователя

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System BIOS Cacheable Enabled
Video BIOS Cacheable Enabled
Memory Hole at 15M-16M Disabled
CPU Latency Timer Disabled
Delayed Transaction Disabled
AGP Mode Select Auto
AGP Graphics Aperture Size 64MB
Menu Level >
↑↓→←
Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
SDRAM Timing Setting
Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The
settings are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area
of system memory usually discusses their memory requirements. The settings are: Enabled
and Disabled.
CPU Latency Timer
During Enabled, A deferrable CPU cycle will only be Deferred after it has been in a Snoop
Stall for 31 clocks and another ADS# has arrived. During Disabled, A deferrable CPU
cycle will be Deferred immediately after the GMCH receives another ADS#.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.