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The Advanced Chipset Features Setup option is used to change the values of the chipset
registers. These registers control most of the system options in the computer.
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Advanced Chipset Features
Item Help
SDRAM CAS Latency Time 3
SDRAM Cycle Time Tras/Trc 6/8
SDRAM RAS-to-CAS Delay 3
SDRAM RAS Precharge Time 3
Special Buffer Strength Enabled
System BIOS Cacheable Enabled
Video BIOS Cacheable Enabled
Memory Hole at 15M-16M Disabled
CPU Latency Timer Disabled
Delayed Transaction Disabled
On-Chip Video Window Size 64MB
Menu Level >
↑↓→←
Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2 and 3.
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.
SDRAM RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2 and 3.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2 and 3.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video BIOS Cacheable
