JBL MS-8, Руководство по обслуживанию

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AUREUS

TMS320DA610, TMS320DA601
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
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Aureus  High-Performance 32-/64-Bit
Audio Digital Signal Processors (DSPs)
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DA610-250 MHz, 2000 MIPS/1500 MFLOPS
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DA601-225 MHz, 1800 MIPS/1350 MFLOPS
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Single DSP Solutions for Multichannel
Audio Applications: A/V and DVD
Receivers, Multi-Zone Receivers, High
Speed Encoder, Simultaneous
Encode/Decode, Surround Headphone,
Speaker Virtualization, Room Correction
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DA601 and DA610 Compatibility Provides a
Scalable Audio Solution Based on a Single
DSP Instruction Set Architecture
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Certified Algorithms:
− Dolby Digital Decoder, Dolby Digital EX,
Dolby Pro Logic IIx, Dolby Pro Logic II
− DTS 5.1, DTS−ES 6.1, DTS Neo:6,
DTS 96/24
− MPEG−2 AAC
− THX Ultra 2
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Supports Other Algorithms Including:
− MP3 CODEC
− WMA CODEC
− SRS Circle Surround II
− Waves’ MaxxBass Technology
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Highly Optimized C/C++ Compiler
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VelociTI  Advanced Very Long Instruction
Word (VLIW) C67x  DSP Core
− Native Instruction Set Support for:
− 32-/64-Bit IEEE 754 Floating-Point
− 32/40/64 & Packed-16-Bit Fixed-Point
− Eight Independent Functional Units:
− Two ALUs (Fixed-Point)
− Four ALUs (Floating- and Fixed-Point)
− Two Multipliers (Floating-/Fixed-Point)
− Fast Time to Market with RISC−Like ISA
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Low-Cost, Two-Level Memory System
− 4K-Byte L1P Plus 4K-Byte L1D Cache
− 256K-Byte L2 Cache/RAM (DA610)
− 128K-Byte L2 Cache/RAM (DA601)
− 512K-Byte L2 ROM (DA610/DA601)
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32-Bit External Memory Interface (EMIF)
Seamlessly Expands Memory Space by
Supporting: SRAM, SDRAM, FLASH,
EPROM, and SBSRAM.
Four External Address Spaces
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16-Bit Host-Port Interface (HPI) Enables
High-Speed Encode/Decode Applications
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Enhanced Direct-Memory-Access (EDMA)
Controller With 16 Independent Channels
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Two Multichannel Audio Serial Ports
(McASPs)
− Independent Dual Zone Audio on a
Single DSP
− 16 Data Pins (32 Channel Stereo)
− Flexible Clocking
− TDM Streams 2-32 Channels per Pin
− Data Formatting Unit Supports Wide
Variety of I2S and Similar Formats
− Integrated Digital Audio Interface
Transmitter (DIT) With Enhanced
Channel Status/User Data
− Extensive Error Checking and Recovery
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Two Inter-Integrated Circuit Bus (I
2
C Bus  )
Multi-Master and Slave Interfaces
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Two Multichannel Buffered Serial Ports
(McBSPs) Supporting:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
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Two 32-Bit General-Purpose Timers
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Two General-Purpose Input/Output
Modules
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On-Chip Oscillator and PLL Module
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IEEE-1149.1 (JTAG
†
)
Boundary-Scan-Compatible
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Package Options:
− 208-Pin PowerPAD
 PQFP (PYP Suffix)
− 272-Pin Ball Grid Array (GDP Suffix)
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0.13- µ m Copper Metal CMOS Process
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3.3-V I/Os, 1.2-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Copyright  2005, Texas Instruments Incorporated
Aureus, VelociTI, C67x, and PowerPAD are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
MS-8
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