JBL MS-8, Руководство по обслуживанию

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64MSDRAMx32_2.fm - Rev. J 12/08 EN
11
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Functional Description
When in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to V
DD
and V
DD
Q.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least
t
RP time; during this time,0 NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least
t
RFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least
t
RFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least
t
MRD time, during which only NOP or DESELECT commands are
allowed.
At this point the DRAM is ready for any valid command.
Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
R
t
RFC loops is achieved.
MS-8
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