Introduction
Copyright IXXAT Automation GmbH
17
IEM Manual, 1.5
1.8.4.1 Communication
Figure 1-2 shows an overview of the part of the DPRAM responsible for the
communication (command, event, service and status).
CMD Buffer
(CLNK)
Status Buffer
(RWWB)
Event (Cbk)
queue
Event queue
(FIFO)
SD queue
HC
à
MC
(FIFO)
SD queue
HC
à
MC
(FIFO)
SD queue
MC
à
HC
(FIFO)
SD queue
MC
à
HC
(FIFO)
Shared
Memory
SHM
IEM
Host
request
response
request
response
callback
request
response
request
response
command
channel
event
service channels (optional)
status
Communication
SD queue
HC
à
MC
(FIFO)
SD queue
MC
à
HC
(FIFO)
indication
indication
SD queue
HC
à
MC
(FIFO)
SD queue
HC
à
MC
(FIFO)
confirmation
confirmation
(trigger from host)
(trigger from module)
Figure 1-2: Schematic overview of communication area at DPRAM
1.8.4.2 Process data
The main concept is that all process data is read/written from/to buffers in the
DPRAM, which are additionally protected by a set of semaphores to ensure
data consistency on large memory blocks. When the buffers are released by
the application processor, the IEM handles all communication standalone
without any interaction from the application processor required.
Cyclic process data
Variables can be readable or writeable, but not read-/writeable. For each
data direction, three buffers are used and swapped after access.
Acyclic process data
Acyclic process data share one buffer; variables can be readable, writeable
and read-/writeable.
Status Buffer
(RWWB)
Status Buffer
(RWWB)
Output Data
Status Buffer
(RWWB)
Status Buffer
(RWWB)
Input Data
Acyclic Data
Shared
Memory
SHM
IEM
Host
Communication
Figure 1-3: Schematic overview of process area at DPRAM
What Figure 1-2 and Figure 1-3 depicted is displayed in the following figure in
more detail. Additionally it shows which API functions of the Ethernet Module
