IXIA AFD2 Скачать руководство пользователя страница 5 | Manualshive

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IXIA AFD2 Скачать руководство пользователя страница 5

Ixia Platform Reference Manual Manual, Release 6.30

15-5

Ixia IRIG-B Auxiliary Function Device (AFD2)

Changing Time Source

2.

Connect the 1PPS and IRIG-B outputs from the IRIG-B receiver to the

AFD2.

3.

Connect the sync and USB cables between AFD2 and the Ixia chassis. On the

front panel of the AFD2,

•

the Pwr OK indicator lights solid,

•

the 1PPS indicator blinks to indicate the signal from the IRIG-B receiveris
good, and

•

the Lock indicator lights solid.

4.

Start the chassis. After starting completely, the IxExplorer resource tree is

displayed as shown in

5.

Note the message regarding timing source, as shown in

.

Figure 15-5. IxServer Start Log Before Attaching AFD2

Changing Time
Source

Any time the clock source is switched, IxServer must be restarted. When the
chassis is switched from Synchronous time source to IRIG-B, or vice-versa, the
following message is displayed as shown in

Figure 15-6. Time Source Change Detection Prompt

You are prompted to restart the IxServer. In this example, the time source was
changed from synchronous to IRIG-B.

1.

Click

OK

and then manually restart IxServer.

IxServer restarts, then detects IRIG-B as the timing source and configure the
chassis as a subordinate, since the chassis is receiving its timing through sync
cable from the AFD2 IRIG-B source. The expected IxServer log messages
are shown in

and

Figure 15-7. IxServer Log - IRIG-B AFD2 Detected

IRIG-B AFD2 is detected and COM6 port is indicated as the communication
channel between chassis and AFD2.

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Содержание AFD2

Страница 1: ...IA AFD2 with integrated IRIG B is designed to provide 12 5 MHz GPS clock with a programmable 80 ns sync pulse to the Optixia chassis The Ixia AFD2 IRIG B receiver is controlled by an Ixia chassis thro...

Страница 2: ...y latency measurements by subtraction of the transmit time stamp from the receive time stamp For large or very remote chassis chains the chassis chain properties provide an offset delay This delay is...

Страница 3: ...e Source Synchronous IRIG B AFD2 IRIG B Mode B000 B000 is straight TTL serial output from the IRIG B receiver B120 B120 is amplitude modulation AM from the IRIG B receiver IRIG B Status Lock Status Lo...

Страница 4: ...n of IRIG B as the timer source the IRIG B status is displayed In Figure 15 3 on page 15 3 the status is locked to the 1PPS signal coming from the IRIG B receiver In the chassis tree view of IxExplore...

Страница 5: ...fore Attaching AFD2 Changing Time Source Any time the clock source is switched IxServer must be restarted When the chassis is switched from Synchronous time source to IRIG B or vice versa the followin...

Страница 6: ...e there is no IRIG B information and the status is Unlocked in the Time Sources tab of Chassis Properties in IxExplorer Figure 15 3 on page 15 3 then one of the following conditions needs to be correc...

Страница 7: ...d by one or more Ixia software users located likewise anywhere in the world Where IRIG B and CDMA sources are used all of the sources must have good quality time values in order for the trigger to be...

Страница 8: ...B Tb Time Absolute T Time Error at any site Terr Lab Ta T1 Tb Lba Tb T2 Ta Delta L Lab Lba Delta L Ta T1 Tb Tb T2 Ta Delta L T1 T2 2 Ta Tb Delta L 2 Ta Tb If Ta T Terr and Tb T Terr Then Delta L 2 T...

Страница 9: ...nd heartbeat is being generated by the IRIG B hardware Pwr OK Green The AFD2 power has been validated Lock Green Indicates that the internal PLL has locked to the 1PPS signal Testing is invalidated if...

Страница 10: ...level shift pulse width coded with BCD CF control functions SBS IRIGB120 1kHz carrier sine wave amplitude modulated with BCD CF control functions SBS Clock 12 5 Mhz GPS System clock Pulse Width 80 ns...

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