IXIA AFD2 Скачать руководство пользователя страница 2

Ixia IRIG-B Auxiliary Function Device (AFD2)

15-2

Ixia Platform Reference Manual Manual, Release 6.30

15

Figure 15-2. AFD2 in a Chassis Chain

The IxExplorer GUI displays the status of the IRIG-B interface to the user. 

Figure 15-3

 shows the Chassis Properties dialog with status information. The 

connection is determined to be either 

locked

 or 

unlocked

. In the Locked state, the 

chassis is locked to IRIG-B time within 150nS. In the unlocked state, the AFD2 
IRIG-B hardware operates to lock its VCXO to 1PPS pulse.

The process of generating the Lock status for the AFD2 consists of getting IRIG-
B time lock and then synchronizing the internal clock to the IRIG-B 1PPS pulse. 
The AFD2 does not enter the ‘Lock’ state until the VCXO lock condition is met.  
In the unlocked state, the chassis in the unlocked chain are not accurately time-
synchronized to the rest of the chain.

In operation, once a chassis chain is constructed and the chassis are 
synchronized, you can clear the timestamps to provide a baseline time for all 
chassis in the chain. The chain operations are then locked until such time that the 
IRIG-B lock is lost by a member of the chain. Data sent from one port in the 
chain to another provides one-way latency measurements by subtraction of the 
transmit time stamp from the receive time stamp.

For large or very remote chassis chains, the chassis chain properties provide an 
offset delay. This delay is defaulted to 5 seconds. For chassis chains where the 
communication delays are significant, as in worldwide or large chains, a longer 
delay should be selected to allow for setup communication delays. The delay is 
the time of a particular chassis operation (for example, start transmit, stop 
transmit) plus the configured delay for any synchronous operation. When an 
operation for the entire chain is executed, this delay is added to the operation. A 
dialog opens indicating that the operation is in process when the delays are 
significant.

The chassis time is taken from any chassis with a IRIG-B interface attached.  The 
setup for the chassis chain requires that all chassis in the chain be locked.  This is 
indicated in the IxExplorer GUI.

The critical operation for a virtual chain is the reset of the System Time Stamps. 
All other actions are dependent on the synchronous execution of this operation. 

Caution:

 A chassis connected to an AFD2 chassis does not operate properly if 

set to Synchronous time source, unless the sync cable is disconnected.

Sync 

Out

Sync 

In

Sync 

In

Ixia XM2

(slave)

Ixia XM2

(slave)

Ixia AFD2 IRIG-B 

Receiver (master)

Sync 

Out

USB cable

provides power and COM3 channel

Customer’s IRIG 

Receiver

Содержание AFD2

Страница 1: ...IA AFD2 with integrated IRIG B is designed to provide 12 5 MHz GPS clock with a programmable 80 ns sync pulse to the Optixia chassis The Ixia AFD2 IRIG B receiver is controlled by an Ixia chassis thro...

Страница 2: ...y latency measurements by subtraction of the transmit time stamp from the receive time stamp For large or very remote chassis chains the chassis chain properties provide an offset delay This delay is...

Страница 3: ...e Source Synchronous IRIG B AFD2 IRIG B Mode B000 B000 is straight TTL serial output from the IRIG B receiver B120 B120 is amplitude modulation AM from the IRIG B receiver IRIG B Status Lock Status Lo...

Страница 4: ...n of IRIG B as the timer source the IRIG B status is displayed In Figure 15 3 on page 15 3 the status is locked to the 1PPS signal coming from the IRIG B receiver In the chassis tree view of IxExplore...

Страница 5: ...fore Attaching AFD2 Changing Time Source Any time the clock source is switched IxServer must be restarted When the chassis is switched from Synchronous time source to IRIG B or vice versa the followin...

Страница 6: ...e there is no IRIG B information and the status is Unlocked in the Time Sources tab of Chassis Properties in IxExplorer Figure 15 3 on page 15 3 then one of the following conditions needs to be correc...

Страница 7: ...d by one or more Ixia software users located likewise anywhere in the world Where IRIG B and CDMA sources are used all of the sources must have good quality time values in order for the trigger to be...

Страница 8: ...B Tb Time Absolute T Time Error at any site Terr Lab Ta T1 Tb Lba Tb T2 Ta Delta L Lab Lba Delta L Ta T1 Tb Tb T2 Ta Delta L T1 T2 2 Ta Tb Delta L 2 Ta Tb If Ta T Terr and Tb T Terr Then Delta L 2 T...

Страница 9: ...nd heartbeat is being generated by the IRIG B hardware Pwr OK Green The AFD2 power has been validated Lock Green Indicates that the internal PLL has locked to the 1PPS signal Testing is invalidated if...

Страница 10: ...level shift pulse width coded with BCD CF control functions SBS IRIGB120 1kHz carrier sine wave amplitude modulated with BCD CF control functions SBS Clock 12 5 Mhz GPS System clock Pulse Width 80 ns...

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