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3.5.9 CPU-TO-PCI IDE Posting
When enabled, the data from processor to PCI IDE can be posted to increase performance.
Otherwise, the cycles are treated as normal I/O write transaction. This field is for the experienced
users only.
Options
Enabled
Disabled (*)
3.5.10 System BIOS Cacheable
When enabled, accesses to the system BIOS will be cached.
Options
Enabled (*)
Disabled
3.5.11 Video BIOS Cacheable
When enabled, access to the video BIOS will be cached.
Options
Enabled
Disabled (*)
3.5.12 Video RAM Cacheable
When enabled, access to the video memory located at A0000H to BFFFFH will be cached.
Options
Enabled
Disabled (*)
3.5.13 8 Bit I/O Recovery Time
This field specifies the number of clocks, which the system will delay after the completion of an 8
bit input/output request.
Options
1 (*) / 2 / 3 / 4 / 5 / 6 / 7 / NA / 8
3.5.14 16 Bit I/O Recovery Time
This field specifies the number of clocks, which the system will delay after the completion of an
16 bit input/output request.
Options
1 (*) / 2 / 3 / NA / 4
