IWILL DP6NS, Руководство пользователя

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When this is ena bled, the chipset will insert one extra clock to the turn -a round of
ba ck-to-ba ck DRAM cycles.
Disabled is the default.
This item a llows you to select the PCI clock type.
PCI CLK/3 PCI clock type
PCI CLK/4 PCI clock type
Cache Features
When ena bled, a ccesses to the system BIOS ROM a ddressed a t F0000H -FFFFFH
a re ca ched, provided tha t the ca che controller is ena bled.
Enabled BIOS access cached
Disabled BIOS access not cached
Disabled is the default.
As with ca ching the System BIOS a bove, ena bling the Video BIOS ca che will
ca use a ccess to video BIOS a ddressed a t C0000H to C7FFFH to be ca ched, if the
ca che controller is a lso ena bled
Enabled Video BIOS access cached
Disabled Video BIOS access not cached
Disabled is the default.
Turn-Around Insertion
ISA Clock
System BIOS
Cacheable
Video BIOS Cacheable