REL1.3
Page 31 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven Edge
Connector
Pin Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
95
USB0_DP/
AG31
IO, DIFF
USB Port1 data positive (OTG).
Note: This pin is connected from
CPU USB0_DP pin.
96
USB_HUB1OUT
_DP
NA
IO, DIFF
USB Host Port0 data positive.
Note: This pin is connected from
On-SOM USB Hub USBDP_DN1
pin.
97
GND
GND
NA
Power
Ground.
98
GND
GND
NA
Power
Ground.
99
e/
DU0_LVDS_CH0
_P
DU0_LVDS_CH0_P/
AJ23
O, 1.8V LVDS
LVDS primary channel differential
pair0 positive.
100
e/
NC
NA
-
NC.
101
eDP0_TX0-/
LVDS_A0-
DU0_LVDS_CH0
_N
DU0_LVDS_CH0_N/
AJ22
O, 1.8V LVDS
LVDS primary channel differential
pair0 negative.
102
eDP1_TX0-/
LVDS_B0-
NC
NA
-
NC.
103
e/
DU0_LVDS_CH1
_P
DU0_LVDS_CH1_P/
AL21
O, 1.8V LVDS
LVDS primary channel differential
pair1 positive.
104
e/
NC
NA
-
NC.
105
eDP0_TX1-/
LVDS_A1-
DU0_LVDS_CH1
_N
DU0_LVDS_CH1_N/
AL22
O, 1.8V LVDS
LVDS primary channel differential
pair1 negative.
106
eDP1_TX1-/
LVDS_B1-
NC
NA
-
NC.
107
e/
DU0_LVDS_CH2
_P
DU0_LVDS_CH2_P/
AJ20
O, 1.8V LVDS
LVDS primary channel differential
pair2 positive.
108
e/
NC
NA
-
NC.
109
eDP0_TX2-/
LVDS_A2-
DU0_LVDS_CH2
_N
DU0_LVDS_CH2_N/
AJ21
O, 1.8V LVDS
LVDS primary channel differential
pair2 negative.
110
eDP1_TX2-/
LVDS_B2-
NC
NA
-
NC.
111
LVDS_PPEN
GPIO_LVDS_PPE
N(GP7_25)
USB1_PWEN/
AE28
O, 3.3V CMOS
Controls LVDS LCD panel power
enable.
Note: GP7_25 is connected to this
pin as GPIO for implementing
LVDS panel power enable.
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