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MITS Janus Time Engine
Page 34 of 39
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20200929
5.1
I/O Connectors
The I/O connectors are identified by name in the images above. Each such connector is
identified below specifying the appropriate mating connector.
Pin outs of certain connectors are shown below
5.1.1
J3 Differential Inputs, PS I/O board
I/O Connector
Type
Where
Mate
AM IRIG in, IRIG DCLS in, CLOCK in
BNC (3)
JTE
Master
Controller
GPS (optional)
SMA
PTP/NTP
RJ45
1PPS (out) (SI), IRIG DCLS (out) (SI),
IRIG AM (out), Clock 1 (B), Clock 2 (A)
HDBNC 75Ω (5)
PS I/O
HDBNC 75Ω
12 VDC in
SAMTEC 4-pin
IPL1-102-01-L-D-RA-K
SAMTEC
IPD1-02-D-K
1PPS, DCLS OUT (differential), 1PPS,
DCLS in (differential)
SAMTEC 6-pin (2)
IPL1-106-01-L-S-RA-K
SAMTEC
IPD1-06-S-K
DIFFERENTIAL INPUTS J3
1
1PPS_IN
2
n/1PPS_IN
3
GROUND
4
GROUND
5
DCLS_IN
6
n/DCLS_IN