— indicates to the CPU that the addressed memory or I/O devices are
not ready for a data transfer;
— the CPU continues to enter a
WAIT
state as long as this signal is
active without refreshing the dynamic memory. Extended
WAIT
periods can prevent the CPU from properly refreshing dynamic
memory.
INT
— interrupt request;
— input, active in “0” logic level;
— interrupt request is generated by I/O devices. The CPU honors a
request at the end of the current instruction if the internal
software-controlled interrupt enable flip-flop (IFF) is enabled and
BUSRQ
is not active.
INT
is normally wired-OR and requires an
external pull-up for these applications.
NMI
— non-maskable interrupt;
— input, negative edge-triggered;
—
NMI
has a higher priority than
INT
.
NMI
is always recognized at the
end of the current instruction, independent of the status of the
interrupt enable flip-flop, and automatically forces the CPU to
restart at location 0066H.
RESET
— CPU reset;
— input, active in “0” logic level;
— initializes the CPU as follows: it resets the interrupt enable flip-flop,
clears the PC and registers I and R, and sets the interrupt status to
Mode 0. During reset time, the address and data bus go to a
high-impedance state, and all control output signals go to the
inactive state; dynamic memory refresh signals are not
generated. Note that
RESET
must be active for a minimum of
three full clock cycles before the reset operation is complete.
BUSRQ
— bus request;
— input, active in “0” logic level;
— bus request has a higher priority than
NMI
and is always recognized
at the end of the current machine cycle.
BUSRQ
forces the CPU
address bus, data bus, and control signals
MREQ
,
IORQ
,
RD
, and
WR
to go to a high-impedance state so that other devices can
control these lines.
BUSRQ
is normally wired-OR and requires an
external pull-up for these applications. Extended
BUSREQ
periods
due to extensive
DMA
operations can prevent the CPU from
properly refreshing dynamic RAMs.
BUSACK
— bus acknowledge;
— output, active in “0” logic level;
— indicates to the requesting device that the CPU address bus, data
bus, and control signals
MREQ
,
IORQ
,
RD
, and
WR
have entered
their high-impedance states. The external circuitry can now control
these lines;
— as long as it is active, dynamic memory refresh signals are not
generated.
7
Содержание CoBra
Страница 20: ...Fig 10 Keyboard schematic 20 ...
Страница 21: ...Fig 11 Keyboard schematic 21 ...
Страница 23: ...Fig 13 Power source schematic 23 ...
Страница 39: ...9 APPENDIX 1 CoBra Microcomputer Schematics 39 ...
Страница 40: ...Fig A1 1 CoBra Microcomputer Central Processing Unit 40 ...
Страница 41: ...Fig A1 2 CoBra Microcomputer Configurator and Selector Circuit 41 ...
Страница 42: ...Fig A1 3 CoBra Microcomputer Read Only Memory Circuit 42 ...
Страница 43: ...Fig A1 4 CoBra Microcomputer DRAM Memory Circuit 43 ...
Страница 44: ...Fig A1 5 CoBra Microcomputer Memory Access Prioritizer and Command Logic 44 ...
Страница 45: ...Fig A1 6 CoBra Microcomputer Video Address Generator Circuit 45 ...
Страница 46: ...Fig A1 7 CoBra Microcomputer Video Address Multiplexer Circuit 46 ...
Страница 47: ...Fig A1 8 CoBra Microcomputer Video Memory Circuit 47 ...
Страница 48: ...Fig A1 9 CoBra Microcomputer Video Sync Pulses Generator Circuit 48 ...
Страница 49: ...Fig A1 10 CoBra Microcomputer Video Signal Shape Generator 49 ...
Страница 50: ...Fig A1 11 CoBra Microcomputer Interfaces 50 ...
Страница 51: ...Fig A1 12 CoBra Microcomputer Voltage Level Adapter Circuits 51 ...
Страница 52: ...Fig A1 13 CoBra Microcomputer Keyboard Interfacing Circuit 52 ...
Страница 53: ...Fig A1 14 CoBra Microcomputer TV Monitor Interfacing Circuit 53 ...
Страница 55: ...10 APPENDIX 2 Flopppy Disk Interface Schematics 55 ...
Страница 56: ...Fig A2 1 Floppy Disk Interface Disk Controller 56 ...
Страница 57: ...Fig A2 2 Floppy Disk Interface Command and Control Signals Generator Circuits 57 ...
Страница 58: ...Fig A2 3 Floppy Disk Interface Write Clock and Digital PLL Circuits 58 ...
Страница 59: ...10 APPENDIX 3 Component Placement on Boards 59 ...
Страница 60: ...60 Fig A3 1 Component Placement on Keyboard Circuit Board ...
Страница 61: ...61 Fig A3 3 Keyboard Circuit Board top layer seen from above keys side ...
Страница 62: ...62 Fig A3 3 Keyboard Circuit Board bottom layer seen from above keys side ...
Страница 63: ...Fig A3 5 Component placement on the floppy interface board 63 ...
