ITCI Brasov CoBra, Описание аппаратуры

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select up to 256 input devices or 256 output devices;
— during the dynamic memory refresh cycle, the contents of the
I and R registers shows up on the address bus, the 7 less
significant bits of the self-incrementing R register being used as a
refresh address.
D0-D7 — the data bus;
— three-state inputs/outputs, active in “1” logic level.
M1 — machine cycle one;
— output, active in “0” logic level;
— together with
MREQ , indicates that the current machine cycle is the
opcode fetch cycle of an instruction execution;
— M1 and IORQ both active indicate the execution of an interrupt
cycle.
MREQ — memory access request;
— three-state output, active in “0” logic level;
— indicates that the address bus holds a valid address for a memory
read of memory write.
IORQ — I/O ports access request;
— three-state output, active in “0” logic level;
— indicates that the lower half of the address bus holds a valid I/O
address for an I/O read or write operation;
— together with M1 , indicates that an interrupt response vector can
be placed on the data bus.
RD — read;
— three-state output, active in “0” logic level;
— indicates that the CPU wants to read data from memory or an I/O
device.
WR — write;
— three-state output, active in “0” logic level;
— indicates that the CPU data bus holds valid data to be stored at the
addressed memory or I/O location.
RFSH — refresh;
— output, active in “0” logic level;
— together with
MREQ , indicates that the lower seven bits of the
system’s address bus can be used as a refresh address to the
system’s dynamic memories.
HALT — halt state;
— output, active in “0” logic level;
— indicates that the CPU has executed a
HALT instruction and is
waiting for either a non-maskable or a maskable interrupt (with the
mask enabled) before operation can resume. During
HALT , the CPU
executes NOP s to maintain memory refresh.
WAIT — wait;
— input, active in “0” logic level;
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