2
Introduction
The ISG CameraLink
TM
Image Grabber Board is a PC PCI daughter card
that features two CameraLink
TM
-Compliant video input connectors, “A”
and “B”. Therefore, it supports image acquisition from one camera and
switching between two cameras in a non-simultaneous mode.
This board receives Gray level digital data from digital sources, such as
the ISG Imager modules and ports the information to a PC host memory
or off-board display memory for further evaluation, analysis and display.
A XILINX Vertex 2 FPGA provides the necessary interface between the
PC PCI Bus and the video interfaces with zero wait state.
CameraLink
TM
Interface:
This interface is based on the industry standard CameraLink
TM
Base
Configuration and consist of the following signals:
§
High Speed Video Signal(s).
§
High Speed Imager Control Signals.
§
Low Speed Serial Communications.
High Speed Video Signals:
The pre-assigned differential LVDS signals receive high-speed pixel data
and pixel qualifier signals from an Imager or camera module. The LVDS
signals are deserialized (8-to-1) at the Imager level, and de-serialized at the
frame grabber by the Channel Link chip set. 33 MHz is the parallel pixel
data rate.
Copyright 2003 Imaging Solutions Group of New York, Inc., All Rights Reserved
Subject to Change Without Notice
