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Open-Q™ 835 Development Kit based on the Snapdragon™ 835 (APQ8098) Processor User Guide Version 1.0

Pin#

CAM0 (J1701)

CAM1 (J1801)

CAM2 (J1901)

Description

MIPI_CSI0_LANE
0_P

MIPI_CSI1_LANE
0_P

MIPI_CSI2_LANE0
_P

Input. MIPI CSI0 / CSI1 / CSI2
data lane 0

GND

Ground

MIPI_CSI0_CLK_ N

MIPI_CSI1_CLK_ N

MIPI_CSI2_CLK_N

Input. MIPI CSI0 / CSI1 / CSI2
clock lane

MIPI_CSI0_CLK_ P

MIPI_CSI1_CLK_ P

MIPI_CSI2_CLK_P

Input. MIPI CSI0 / CSI1 / CSI2
clock lane

GND

Ground

MIPI_CSI0_LANE
1_N

MIPI_CSI1_LANE
1_N

MIPI_CSI2_LANE1
_N

Input. MIPI CSI0 / CSI1 / CSI2
data lane 1

MIPI_CSI0_LANE
1_P

MIPI_CSI1_LANE
1_P

MIPI_CSI2_LANE1
_P

Input. MIPI CSI0 / CSI1 / CSI2
data lane 1

GND

Ground

MIPI_CSI0_LANE
2_N

MIPI_CSI1_LANE
2_N

MIPI_CSI2_LANE2
_N

Input. MIPI CSI0 / CSI1 / CSI2
data lane 2

MIPI_CSI0_LANE
2_P

MIPI_CSI1_LANE
2_P

MIPI_CSI2_LANE2
_P

Input. MIPI CSI0 / CSI1 / CSI2
data lane 2

GND

Ground

MIPI_CSI0_LANE
3_P

MIPI_CSI1_LANE
3_P

MIPI_CSI2_LANE3
_P

Input. MIPI CSI0 / CSI1 / CSI2
data lane 3

MIPI_CSI0_LANE

3_N

MIPI_CSI1_LANE

3_N

MIPI_CSI2_LANE3

Input. MIPI CSI0 / CSI1 / CSI2
data lane 3

GND

Ground

CCI_I2C_SDA1
(APQ_GPIO19)

Output / Input. Connected to
APQ8098 GPIO19. Default use
is for camera CCI1 I2C data
interface

CCI_I2C_SCL1
(APQ_GPIO20)

Output. Connected to APQ8098
GPIO20. Default use is for
camera CCI1 I2C clock interface

CAM_IRQ
(APQ_GPIO26)

CAM_IRQ (APQ_GPIO26)

Input. Connected to APQ8098
GPIO26. CAM_IRQ signal

CAM0_MCLK3
(APQ_GPIO16)

CAM1_MCLK3
(APQ_GPIO16)

CAM2_MCLK3
(APQ_GPIO16)

Output. Connected to APQ8098
GPIO16. Default use is for
camera master clock. Maximum
24MHz

MB_ELDO_CAM0
_DVDD

MB_ELDO_CAM1
_DVDD

MB_ELDO_CAM2_DVDD

Power output. Connected to
external LDO regulator. Default
is +1.2V. Maximum current
500mA

40,
41

MB_VREG_5P0

Power output. 5V Power supply.
Maximum 700mA

Note:

A connection from the camera connectors on the carrier board to the Intrinsyc

camera adapter board is established by a 41-pin cable assembly from JAE Electronics (part
number JF08R0R041020MA)

The following table shows the combinations of camera usage for different use cases

Содержание Open-Q 835

Страница 1: ...the Agreement solely in support of your permitted use of the Open Q 835 Development Kit under the Agreement Distribution of this document is strictly prohibited without the express written permission...

Страница 2: ...ight Intrinsyc Technologies Corporation IDENTIFICATION Document Title Open Q 835 Development Kit based on the Snapdragon 835 APQ8098 Processor User Guide Document Number ITC 01IMP1283 UG 001 Version 1...

Страница 3: ...ification 16 3 7 4 Processor Board RF Specification for WIFI BT 17 3 8 Open Q 835 Carrier Board 18 3 8 1 Dip switch S10 Configuration Options 19 3 8 2 Carrier Board Expansion Connectors 21 3 8 3 DC Po...

Страница 4: ...Open Q 835 Development Kit based on the Snapdragon 835 APQ8098 Processor User Guide Version 1 0 4 Copyright Intrinsyc Technologies Corporation 3 8 23 GNSS Card 41...

Страница 5: ...sed on the Snapdragon 835 APQ8098 Processor For more background information on this development kit visit www intrinsyc com 1 2 Scope This document will cover the following items on the Open Q 835 Dev...

Страница 6: ...erial interfaces like UART SPI I2C UIM BT LE Bluetooth Low Energy CSI Camera Serial Interface DSI MIPI Display Serial Interface EEPROM Electrically Erasable Programmable Read only memory eMMC Embedded...

Страница 7: ...Q8098 Processor User Guide Version 1 0 7 Copyright Intrinsyc Technologies Corporation UART Universal Asynchronous Receiver Transmitter UFS Universal Flash Storage UIM User Identity module USB Universa...

Страница 8: ...ug UART Header 25 Figure 10 J2102 Debug UART over USB 26 Figure 11 J2101 JTAG Header 26 Figure 12 J2501 Sensor Expansion Header 27 Figure 13 J2502 Gen 10 Sensor Connector Samtec QSH 030 series 28 Figu...

Страница 9: ...s and Usage 21 Table 3 8 5 J1001 Battery Header Pin out 24 Table 3 8 6 J10901 Pin out 25 Table 3 8 7 J2103 Debug UART Header Pin out 25 Table 3 8 8 J2101 JTAG Header Pin out 26 Table 3 8 9 Sensor Expa...

Страница 10: ...the requirements of a commercially available consumer device including those requirements specified in the European Union directives applicable for Radio devices being placed on the market FCC equipme...

Страница 11: ...Corporation o Open Q 835 Processor board with the Snapdragon 835 APQ8098 processor main CPU board o Mini ITX form factor carrier board for I O and connecting with external peripherals o GNSS Card o 5...

Страница 12: ...nsor boards and other accessories sales intrinsyc com 3 5 Hardware Identification Label Labels are present on the CPU board The following information is conveyed on these two boards Processor board Se...

Страница 13: ...the interconnectivity and peripherals on the development kit Figure 3 Open Q 835 Processor board Carrier Board Block Diagram 2x32 LPDDR4x PoP WiGig60 Processor card 3 4 3 PM8998 DSI WCN3990 Via Analo...

Страница 14: ...application processor LPDDR4 up to 1866MHz 4GB RAM POP PMI8998 PM8998 PMIC for Peripheral LDOs Boost Regulators WCN3990 Wi Fi BT FM combo chip over SLIMbus Analog IQ UART PCM 128 GB UFS 2 1 WCD9341 A...

Страница 15: ...here all the processing occurs It is connected to the carrier board via two 100 pin Hirose 240 pin connectors The purpose of these connectors is to bring out essential signals such that other peripher...

Страница 16: ...ART SLIMbus WCN3990 Wi Fi BT FM Combo Chip Support BT 5 0 HS and backward compatible with BT 1 x 2 x EDR GNSS via WTR5975 Qlink Qualcomm Proprietary Protocol GNSS Frontend GPS GLONASS COMPASS Galilei...

Страница 17: ...y This antenna connector is connected to carrier board PCB antenna via a coaxial cable ANT0 is a standard dual band antenna from 2 4 GHz to 5 GHz and BT Antenna 1 Antenna 1 is for WCN3990 to provide W...

Страница 18: ...ed for connecting different peripherals The following are the mechanical properties of the carrier board Table 3 8 1 Open Q 835 Carrier Board Mechanical Properties Dimensions 289 cm2 170mm x 170mm For...

Страница 19: ...HDOG _DISABLE S2301 2 Enables WATCHDOG_DISABLE when DIP switch turned on Controlled by APQ GPIO 101 Default out of the box configuration is OFF BOOT_CONFIG 1 S2301 3 Enables APQ boot configuration 1 w...

Страница 20: ...Default HUB reset control is from s w hardware rework is needed to enable this function MSM_PS_HOLD S2302 4 Enables the JTAG_PS_HOLD mode when DIP switch turned on Default out of the box configuratio...

Страница 21: ...y NFC Board Header 20 pin NFC expansion connectors NA NA 3 Digital Microphone via audio input expansion header Audio expansion Supported using WCD9341 Digital Audio header For Digital audio input for...

Страница 22: ...i PCI express cards for internal use only not supported CSI Camera connectors 3 x CSI port connector with CLK GPIOS CCI Supports 3 x Camera interfaces via three separate connectors 3 x MIPI CSI each 4...

Страница 23: ...red correctly user can monitor the current going into the Processor board via the power probe header J0901 see section below Figure 7 J0701 12V DC Power Jack The Processor board has 2 PMIC modules Fun...

Страница 24: ...n out Description Signal Pin Note Processor board Battery negative supply terminal VBAT Minus VBAT J1001 1 NC NC J1001 2 Internal battery pack temperature BATT_THERM The recommended battery has a 10K...

Страница 25: ...igure 9 J2103 Debug UART Header The UART header and supporting circuitry does not come preinstalled To have access to the debug UART a 3 pin header needs to be installed as well as the supporting circ...

Страница 26: ...main processor by which users can connect a JTAG Lauterbach USB Wiggler 20 pin ARM JTAG NOTE It does not provide software support for JTAG Table 3 8 8 J2101 JTAG Header Pin out Description Signal Pin...

Страница 27: ...rupt input to processor via GPIO117 ACCEL_INT_N J2501 2 SSC I2C 3 serial clock SSC_I2C_3_SCL J2501 3 Cap interrupt input to processor via GPIO123 CAP_INT_N J2501 4 Sensor reset signal from processor t...

Страница 28: ...n provide two full BLSP7 and BLSP5 for UART SPI I2C UIM Please refer to the schematic and consider the power before connecting anything to this header Note that there is an unpopulated Gen 10 connecto...

Страница 29: ...01 10 1 8V Voltage regulator supply max 150mA via PM8998 VREG_L9A_1P8 J2401 11 BLSP8 I2C Bus 8 I2C SDA line BLSP8_I2C_SDA J2401 12 1 8V Voltage regulator supply max 150mA via PM8998 VREG_S4A_1P8 J2401...

Страница 30: ..._IN1_N J1601 2 Analog MIC3 positive differential input CDC_IN3_P J1601 3 Analog MIC3 negative differential input CDC_IN3_N J1601 4 MIC bias output voltage 1 MIC_BIAS1 J1601 5 MIC bias output voltage 3...

Страница 31: ...audio line out 1 positive differential output LINE_OUT1_P J1602 1 Analog audio line out 1 negative differential output LINE_OUT1_N J1602 2 Analog audio line out 2 positive differential output LINE_OU...

Страница 32: ...12V J1602 18 5 0V output power supply MB_VREG_ 5P0 J1602 19 GND GND J1602 20 3 8 14 On Board PCB WLAN Antenna The Open Q 835 carrier board has two on board WLAN PCB antennas that connects to the WiFi...

Страница 33: ...re 0ohm jumpers for user to choose to use external GPS antenna via the SMA connector The option pads are at the antenna end before the GPS LNA input see table below for details Table 3 8 13 GPS Antenn...

Страница 34: ...upport external backlight driver control and power PMI8998 backlight driver supports three LED strings of up to 30mA each with 28V maximum boost voltage The Open Q 835 development platform can support...

Страница 35: ...to the carrier schematic and display board tech note when designing a custom display board DSI o 2 x 4 lane DSI Backlight o Built in backlight WLED driver on PMI8998 WLED driver supports up to 28 5V...

Страница 36: ...rier 3 3V up to 0 5A Carrier 5 V up to 1 5A Carrier 12 V up to 0 5A The Intrinsyc AMOLED Display Adapter board part number TBD is an additional PCB that mates with the display connector J1301 on the c...

Страница 37: ...D display that comes with the display adaptor board As shown in the block diagram below the MIPI DSI0 lines which come from the 100 pin ERM8 connector directly connects to the LCD panel See the sectio...

Страница 38: ...ors The Open Q 835 development kit supports three 4 lane MIPI CSI camera interfaces via three separate JAE 41 pin connectors The following are some features of the camera connectors 3 x 4 lane MIPI CS...

Страница 39: ...98 VREG_LVS1A switch output Default is 1 8V Maximum current 300mA 11 GND GND GND Ground 12 FLASH_STROBE _EN APQ_GPIO21 FLASH_STROBE _EN APQ_GPIO21 FLASH_STROBE_ EN APQ_GPIO21 Output Connected to APQ80...

Страница 40: ...2 data lane 3 33 MIPI_CSI0_LANE 3_N MIPI_CSI1_LANE 3_N MIPI_CSI2_LANE3 _N Input MIPI CSI0 CSI1 CSI2 data lane 3 34 GND GND GND Ground 35 CCI_I2C_SDA1 APQ_GPIO19 CCI_I2C_SDA1 APQ_GPIO19 CCI_I2C_SDA1 AP...

Страница 41: ...D 4 lane 3D use case Dual 4 lane configuration CSI 2 Up to 1 lane 3D 1 lane 3D use case Dual 1 lane configuration CSI0 CSI1 CSI2 Up to 4 lane Three 4 lane CSI 4 4 4 or 4 4 2 1 CPHY Three 3 trio CPHY1...

Страница 42: ...ation both digital and RF interfaces Digital interface is required for configuration and status for the APQ8098 processor The following are the operating frequencies for WTR5975 GPS 1574 42 MHz 1576 4...

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