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©2005, Intersil Corp.
Page 13/16
Ver. 1.1, 12/19/05
Operation
The DVI monitor should now be displaying the image being received by the AFE.
At this point, all the registers of the ISL98001 can be adjusted. For example, the PLL Phase register
(0x10) can be adjusted to find the optimum sampling phases for the signal.
The gain control registers (0x06 – 0x08) and the offset control registers (0x09 – 0x0B) can be
adjusted for contrast and brightness control.
The Automatic Black Level Compensation (ABLC, register 0x17) function can be disabled to compare
the image with and without ABLC
Please refer to the ISL98001 datasheet for more information on the ISL98001 and its configuration
options.
Notes
•
All registers can be read by pressing the “Read All Registers” button.
•
Registers 0x00 – 0x02 are read-only.
•
The HTOTAL value is not latched by the ISL98001 until the LSB (0x0F) is written (i.e. writes to
the MSB only will not change the HTOTAL used by the ISL98001).
•
The box at the bottom of the display can be used to read or write any register, including some
production test registers. These registers are not needed in normal operation of the Analog
Front End and are therefore not documented.
