Intel Xeon Processor E5-1600, Техническое описание

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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families 43
Datasheet Volume One
2.5.2.6.7 Accumulated DRAM Energy Read
This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs
within all the channels or all the DIMMs within just a specified channel. The parameter
field is used to specify the channel index. Units used are defined as per the Package
Power SKU Unit read described in
Section 2.5.2.6.11 . This information is tracked by a
32-bit counter that wraps around. The channel index in Figure 2-17 is specified as per
the index encoding described in Table 2-7 . A channel index of 0x00FF is used to specify
the “all channels” case. While Intel requires reading the accumulated energy data at
least once every 16 seconds to ensure functional correctness, a more realistic polling
rate recommendation is once every 100 mS for better accuracy. This feature assumes a
200W memory capacity. In general, as the power capability decreases, so will the
minimum polling rate requirement.
When determining energy changes by subtracting energy values between successive
reads, Intel advocates using the 2’s complement method to account for counter wrap-
arounds. Alternatively, adding all ‘F’s (‘0xFFFFFFFF’) to a negative result from the
subtraction will accomplish the same goal.
2.5.2.6.8 DRAM Power Info Read
This read returns the minimum, typical and maximum DRAM power settings and the
maximum time window over which the power can be sustained for the entire DRAM
domain and is inclusive of all the DIMMs within all the memory channels. Any power
values specified by the power limiting entity that is outside of the range specified
through these settings cannot be guaranteed. Since this data is 64 bits wide, PECI
facilitates access to this register by allowing two requests to read the lower 32 bits and
upper 32 bits separately as shown in
Table 2-6 . Power and time units for this read are
defined as per the Package Power SKU Unit settings described in Section 2.5.2.6.11 .
Figure 2-16. Processor DRAM Channel Temperature
15 7 0
Channel Temperature Data
Channel 3
Maximum
Temperature
(in Degrees C)
Channel 2
Maximum
Temperature
(in Degrees C)
Channel 1
Maximum
Temperature
(in Degrees C)
Channel 0
Maximum
Temperature
(in Degrees C)
8 16 23 24 31
Figure 2-17. Accumulated DRAM Energy Data
0
Accumulated DRAM Energy Data
Accumulated DRAM Energy
31
15
2
Parameter format
Reserved Channel Index
3 0