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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

27

Datasheet Volume One

Interfaces

2.2.1.1

Transaction Layer

The upper layer of the PCI Express* architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.

2.2.1.2

Data Link Layer

The middle layer in the PCI Express* stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets which are used for Link management functions.

2.2.1.3

Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express* Link at a frequency and
width compatible with the remote device.

2.2.2

PCI Express* Configuration Mechanism

The PCI Express* link is mapped through a PCI-to-PCI bridge structure.

PCI Express* extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the

Conventional PCI Specification

. PCI Express*

configuration space is divided into a PCI-compatible region (which consists of the first

Figure 2-2. Packet Flow through the Layers

Framing

Sequence

Number

Header

Data

LCRC

ECRC

Framing

Transaction Layer

Physical Layer

Data Link Layer

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Содержание Xeon Processor E5-1600

Страница 1: ...Reference Number 326508 Revision 002 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One May 2012...

Страница 2: ...distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may...

Страница 3: ...1 2 System Memory Timing Support 25 2 2 PCI Express Interface 26 2 2 1 PCI Express Architecture 26 2 2 2 PCI Express Configuration Mechanism 27 2 3 DMI2 PCI Express Interface 28 2 3 1 DMI2 Error Flow...

Страница 4: ...fications 97 4 3 System Memory Power Management 98 4 3 1 CKE Power Down 98 4 3 2 Self Refresh 98 4 3 3 DRAM I O Power Management 99 4 4 DMI2 PCI Express Power Management 99 5 Thermal Management Specif...

Страница 5: ...cifications 182 7 10 2 I O Signal Quality Specifications 182 7 10 3 Intel QuickPath Interconnect Signal Quality Specifications 182 7 10 4 Input Reference Clock Signal Quality Specifications 182 7 10 5...

Страница 6: ...DRAM Power Info Read Data 44 2 19 DRAM Power Limit Data 45 2 20 DRAM Power Limit Performance Data 45 2 21 CPUID Data 49 2 22 Platform ID Data 49 2 23 PCU Device ID 49 2 24 Maximum Thread ID 50 2 25 Pr...

Страница 7: ...18 DTS 6 Core 60W Thermal Profile 1U 122 5 19 Tcase 4 Core 130W Thermal Profile 2U 123 5 20 DTS 4 Core 130W Thermal Profile 2U 124 5 21 Tcase 4 Core 130W 1S WS Thermal Profile 126 5 22 DTS 4 Core 130W...

Страница 8: ...kgConfig Response Definition 37 2 6 RdPkgConfig WrPkgConfig DRAM Thermal and Power Optimization Services Summary 39 2 7 Channel DIMM Index Decoding 41 2 8 RdPkgConfig WrPkgConfig CPU Thermal and Power...

Страница 9: ...l Specifications Workstation Server Platform 125 5 21 4 Core 130W 1S WS Thermal Profile Table 127 5 22 Tcase 4 2 Core 80W Thermal Specifications 1U 127 5 23 4 2 Core 80W Thermal Profile Table 1U 129 5...

Страница 10: ...eference Clock BCLK 0 1 DC Specifications 176 7 19 SMBus DC Specifications 176 7 20 JTAG and TAP Signals DC Specifications 177 7 21 Serial VID Interface SVID DC Specifications 177 7 22 Processor Async...

Страница 11: ...r E5 1600 E5 2600 E5 4600 Product Families 11 Datasheet Volume One Revision History Revision Number Description Revision Date 001 Initial Release March 2012 002 Added Intel Xeon Processor E5 4600 Prod...

Страница 12: ...12 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

Страница 13: ...igher performance easier validation and improved x y footprint The Intel Xeon processor E5 1600 product family and the Intel Xeon processor E5 2600 product family are designed for Efficient Performanc...

Страница 14: ...Processor Feature Details Up to 8 execution cores Each core supports two threads Intel Hyper Threading Technology up to 16 threads per socket Figure 1 1 Intel Xeon Processor E5 2600 Product Family on...

Страница 15: ...Advanced Encryption Standard Instructions Intel AES NI Intel 64 Architecture Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Advanced Vector Ex...

Страница 16: ...ckstep mode Lockstep mode where channels 0 1 and channels 2 3 are operated in lockstep mode The combination of memory channel pair lockstep and memory mirroring is not supported Data scrambling with a...

Страница 17: ...synchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space The remaining portion...

Страница 18: ...1 VCm and VCp 1 2 4 Intel QuickPath Interconnect Intel QPI Compliant with Intel QuickPath Interconnect v1 1 standard packet formats Implements two full width Intel QPI ports Full width port includes 2...

Страница 19: ...channel between a PECI client the processor and a PECI master the PCH Supports operation at up to 2 Mbps data transfers Link layer improvements to support additional services and higher efficiency ove...

Страница 20: ...ybrid OLTT CLTT mode Fan speed control with DTS Two integrated SMBus masters for accessing thermal data from DIMMs New Memory Thermal Throttling features via MEM_HOT_C 01 23 _N signals Running Average...

Страница 21: ...ency if the part is operating under power temperature and current specifications limits of the Thermal Design Power TDP This results in increased performance of both single and multi threaded applicat...

Страница 22: ...tions are measured at the processor die pads unless otherwise noted RDIMM Registered Dual In line Memory Module Rank A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These d...

Страница 23: ...ts Sheet 1 of 2 Document Location Intel Xeon Processor E5 Product Family Datasheet Volume Two http www intel com Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design...

Страница 24: ...vailable by the publication date of this document Intel Virtualization Technology Specification for Directed I O Architecture Specification http download intel com technolog y computing vptech Intel r...

Страница 25: ...rms support ECC registered DIMMs with a maximum of three DIMMs per channel allowing up to eight device ranks per channel ECC and non ECC unbuffered DIMMs with a maximum of two DIMMs per channel thus a...

Страница 26: ...m PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the rece...

Страница 27: ...P error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consum...

Страница 28: ...setting of the SOCKET_ID 1 0 and FRMAGENT signal for processors not connected to a PCH Note Only DMI2 x4 configuration is supported 2 3 1 DMI2 Error Flow DMI2 can only generate SERR in response to err...

Страница 29: ...port ancillary features required in the transmission and receipt of the 1s and 0s The unit of transfer at the Physical layer is 20 bits which is called a Phit for Physical unit The Link layer is respo...

Страница 30: ...rating conditions and configuration information The PECI bus offers A wide speed range from 2 Kbps to 2 Mbps CRC check byte used to efficiently and atomically confirm accurate data delivery Synchroniz...

Страница 31: ...egisters in the processor PCI configuration space Details are covered in Section 2 5 2 10 2 5 1 3 Processor Interface Tuning and Diagnostics The processor Intel Interconnect Built In Self Test Intel I...

Страница 32: ...cessor PECI clients support the GetDIB command 2 5 2 2 1 Command Format The GetDIB format is as follows Write Length 0x01 Read Length 0x08 Command 0xf7 Figure 2 3 Ping Byte Byte Definition 0 Client Ad...

Страница 33: ...ommand suites or response codes from the client Revision Number is always reported in the second byte of the GetDIB response The Major Revision number in Figure 2 7 always maps to the revision number...

Страница 34: ...NTROL may be extracted from the processor by issuing a PECI RdPkgConfig command as described in Section 2 5 2 4 or using a RDMSR instruction TCONTROL application to fan speed control management is def...

Страница 35: ...for more details on processor specific services supported through this command 2 5 2 4 1 Command Format The RdPkgConfig format is as follows Write Length 0x05 Read Length 0x05 dword Command 0xa1 Desc...

Страница 36: ...al management functions Typical PCS write services supported by the processor may include power limiting thermal averaging constant programming and so on Refer to Section 2 5 2 6 for more details on p...

Страница 37: ...confidence that the data it received from the host is correct This is especially critical where the consumption of bad data might result in improper or non recoverable operation Note The 2 byte param...

Страница 38: ...ly only to the memory connected to the specific processor PECI client in question and not the overall platform memory in general For estimating DRAM thermal information in closed loop throttling mode...

Страница 39: ...e estimation N A DIMM Ambient Temperature Write Read 19 0x0000 Absolute temperature in Degrees C to be used as ambient temperature reference N A Read ambient temperature reference for activity based r...

Страница 40: ...for translation of DRAM energy changes to corresponding temperature changes and may be derived from actual platform characterization data The Scaling Factor is used to convert memory transaction info...

Страница 41: ...PECI host to read the temperature of all the DIMMs within a channel up to a maximum of three DIMMs This read is not limited to platforms using a particular memory temperature source or temperature est...

Страница 42: ...alue The ambient temperature assumes a single value for all memory channel DIMM locations and does not account for possible temperature variations based on DIMM location 2 5 2 6 6 DRAM Channel Tempera...

Страница 43: ...vocates using the 2 s complement method to account for counter wrap arounds Alternatively adding all F s 0xFFFFFFFF to a negative result from the subtraction will accomplish the same goal 2 5 2 6 8 DR...

Страница 44: ...cified in the DRAM power settings In general any tuning of the power settings is done by polling the voltage regulators supplying the DIMMs 2 5 2 6 9 DRAM Power Limit Data Write Read This feature allo...

Страница 45: ...nband DRAM power limiting accesses by setting bit 31 of the DRAM_POWER_LIMIT MSR or DRAM_PLANE_POWER_LIMIT CSR to 1 2 5 2 6 10 DRAM Power Limit Performance Status Read This service allows the PECI hos...

Страница 46: ...or signature 0x0001 Platform ID Used to ensure microcode update compatibility with processor MSR 17h IA32_PLATFORM_ID 0x0002 PCU Device ID Returns the Device ID information for the processor Power Con...

Страница 47: ...CHOT_N assertion and Critical Temperature MSR 1B1h IA32_PACKAGE_THERM_STATUS Thermal Averaging Constant Write Read 21 0x0000 Thermal Averaging Constant N A Reads the Thermal Averaging Constant N A The...

Страница 48: ..._PERF_STATUS Efficient Performance Indicator Read 06 0x0000 Number of productive processor cycles N A Read number of productive cycles for power budgeting purposes N A ACPI P T Notify Write Read 33 0x...

Страница 49: ...64 and IA 32 Architectures Software Developer s Manual SDM Volumes 1 2 and 3 for more information PCU Device ID This information can be used to uniquely identify the processor power control unit PCU d...

Страница 50: ...set if the package asserted CAT_ERR_N The CAT_ERR_N may be used to signal the occurrence of a MCERR or IERR 2 5 2 6 13 Package Power SKU Unit Read This feature enables the PECI host to read the units...

Страница 51: ...package power in bits 46 32 is the maximum value of the Power Limit2 field The minimum package power in bits 30 16 is applicable to both the Power Limit1 Power Limit2 fields and corresponds to a mode...

Страница 52: ...kage states C3 or deeper 2 5 2 6 16 Accumulated Run Time Read This read returns the total time for which the processor has been executing with a resolution of 1 mS per count This is tracked by a 32 bi...

Страница 53: ...ufacturing process variations The Temperature Target read also returns the processor TCONTROL value TCONTROL is returned in standard PECI temperature format and represents the threshold temperature us...

Страница 54: ...a lowered power state due to TCC activation The returned data includes the time required to ramp back up to the original P state target after TCC activation expires This timer does not include TCC act...

Страница 55: ...ill accomplish the same goal 2 5 2 6 25 Power Limit for the VCC Power Plane Write Read This feature allows the PECI host to program the power limit over a specified time or control window for the proc...

Страница 56: ...mming the Control Time Window in bits 23 17 2 5 2 6 26 Package Power Limits For Multiple Turbo Modes This feature allows the PECI host to program two power limit values to support multiple turbo modes...

Страница 57: ...5 2 6 9 should be applied when programming the Control Time Window bits 23 17 for power limit 1 in Figure 2 36 The Control Time Window for power limit 2 can be directly programmed into bits 55 49 in u...

Страница 58: ...otifies the OS using the ACPI Notify mechanism as supported by the _PPC or performance present capabilities object The BMC then notifies the processor PCU using the PECI ACPI P T Notify service by pro...

Страница 59: ...nored The Core ID read may not return valid data until at least 1 mS after the IERR assertion Note Reads to caching agents that are not enabled will return all zeroes Refer to the debug handbook for d...

Страница 60: ...IA MSR space refers to a specific logical processor within the CPU The Processor ID always refers to the same physical location in the processor silicon regardless of configuration as shown in the ex...

Страница 61: ...ata field defined in Figure 2 43 are sent in standard PECI ordering with LSB first and MSB last Figure 2 42 Processor ID Construction Example Figure 2 43 RdIAMSR T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0...

Страница 62: ...ate CC 0x81 Response timeout The processor is not able to allocate resources for servicing this command at this time Retry is appropriate CC 0x82 The processor hardware resources required to service t...

Страница 63: ...0x40 0x0 0xF 0x0282 IA32_MC2_CTL2 0x0 0xF 0x0424 IA32_MC9_CTL 0x0 0xF 0x043F IA32_MC15_MISC 0x0 0xF 0x0409 IA32_MC2_STATUS 0x0 0xF 0x0289 IA32_MC9_CTL2 0x0 0xF 0x0440 IA32_MC16_CTL 0x0 0xF 0x040A IA3...

Страница 64: ...rogrammable by BIOS The bus number for PCH devices may be obtained by reading the CPUBUSNO CSR Refer to the Intel Xeon Processor E5 Product Family Datasheet Volume Two document for details on this reg...

Страница 65: ...PECI originators can access this space even prior to BIOS enumeration of the system buses There is no read restriction on accesses to locked registers PCI configuration addresses are constructed as s...

Страница 66: ...sponse is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure The PECI client response can also vary depending on the address and...

Страница 67: ...ill abort the write and will always respond with a bad write FCS PCI Configuration addresses are constructed as shown in Figure 2 46 The write command is subject to the same address configuration rule...

Страница 68: ...Host ID 7 1 Retry 0 4 8 Read Length 0x01 5 6 Cmd Code 0xe5 10 11 Client Address 9 LSB PCI Configuration Address MSB LSB Data 1 2 or 4 bytes MSB 7 Table 2 14 WrPCIConfigLocal Response Definition Respon...

Страница 69: ...RESET_N de assertion as shown in Figure 2 49 PECI will be fully functional with all services including core accesses being available when the core comes out of reset upon completion of the RESET micro...

Страница 70: ...rough the settings of the SOCKET_ID 1 0 signals Each processor socket in the system requires that the two SOCKET_ID signals be configured to a different PECI addresses Strapping the SOCKET_ID 1 0 pins...

Страница 71: ...impact on the package C state The PECI client will successfully return data without impacting package C state if the resources needed to service the command are not in a low power state If the resour...

Страница 72: ...client no longer participating in the response The processor client is otherwise reset to a default configuration The assertion of the CPU_ONLY_RESET signal does not reset the processor PECI client A...

Страница 73: ...ly the Ping GetTemp and GetDIB PECI commands may be serviced All other processor PECI services will be unavailable and further debug of the processor error status will not be possible If the PECI clie...

Страница 74: ...ed includes an Unknown Invalid Illegal Request completion code 0x90 then the command is unsupported Enumerating known commands without real execution context data or attempting undefined commands is d...

Страница 75: ...s or fail Bit 7 is always set on a command that did not complete successfully and is cleared on a passing command Note The codes explicitly defined in Table 2 22 may be useful in PECI originator respo...

Страница 76: ...etation The resolution of the processor s Digital Thermal Sensor DTS is approximately 1 C which can be confirmed by a RDMSR from the IA32_THERM_STATUS MSR where it is architecturally defined The MSR r...

Страница 77: ...ring The processor digital thermal sensor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals Coupled...

Страница 78: ...78 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

Страница 79: ...Intel VT for Directed I O Intel VT d adds processor and uncore implementations to support and improve I O virtualization performance and robustness The Intel VT d spec and other Intel VT documents ca...

Страница 80: ...tor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software Pause...

Страница 81: ...r improved performance Due to shorter page walks allows hardware optimization for IOTLB Transition latency reductions expected to improve virtualization performance without the need for VMM enabling T...

Страница 82: ...part of the trust chain 3 2 3 Intel Advanced Encryption Standard Instructions Intel AES NI These instructions enable fast and secure data encryption and decryption using the Intel AES New Instruction...

Страница 83: ...t allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power temperature and current limits The result is increased perfor...

Страница 84: ...es power while delivering advanced power management capabilities at the rack group and data center level Providing the highest system level performance per watt with Automated Low Power States and Int...

Страница 85: ...ions OS context management for vector widths beyond 256 bits is streamlined Efficient instruction encoding allows unlimited functional enhancements Vector width support beyond 256 bits 256 bit Vector...

Страница 86: ...Technologies 86 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

Страница 87: ...ackage C state 2 the additional factors that will restrict the state from going any deeper and 3 the actions taken with respect to the Ring Vcc PLL state and LLC Table 4 3 lists the processor core C s...

Страница 88: ...ore VCC Context CC0 Running On Coherent Active Maintained CC1 Stopped On Coherent Active Maintained CC1E Stopped On Coherent Request LFM Maintained CC3 Stopped On Flushed to LLC Request Retention Main...

Страница 89: ...ped Power Down with IBT Off Table 4 5 DMI2 PCI Express Link States State Description L0 Full on Active transfer state L1 Lowest Active State Power Management ASPM Longer exit latency Table 4 4 System...

Страница 90: ...tablished the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling th...

Страница 91: ...power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state requests using the legacy method of I O reads from th...

Страница 92: ...eature which triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF 4 2 4 Core C states The following are general rules for all core C states unless specified otherwise A core C...

Страница 93: ...hes core architecture state is saved to the uncore Once the core state save is completed core voltage is reduced to zero During exit the core is powered on and its architectural state is restored 4 2...

Страница 94: ...r its previous package state If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to it...

Страница 95: ...ions are taken in the package C1 state However if the C1E substate is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage Au...

Страница 96: ...cy requirements are too stringent for the package to take any power saving actions If the exit latency requirements are high enough the package will transition to C3 or C6 depending on the state of th...

Страница 97: ...lists the processor package C state power specifications for various processor SKUs Notes 1 Package C1E power specified at Tcase 60 C 2 Package C3 C6 power specified at Tcase 50 C 4 3 System Memory Po...

Страница 98: ...l DDR clock is disabled and the DDR power is significantly reduced The DDR defines three levels of power down Active power down Precharge power down fast exit Precharge power down slow exit 4 3 2 Self...

Страница 99: ...om PLL indicating that the memory controller can start working again 4 3 3 DRAM I O Power Management Unused signals are tristated to save power This includes all signals associated with an unused memo...

Страница 100: ...Power Management 100 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

Страница 101: ...operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TCASE specifications as defined by the applicable therma...

Страница 102: ...tuality the processor case temperature will not reach this value due to TCC activation For Embedded Servers Communications and storage markets Intel has plan SKU s that support Thermal Profiles with n...

Страница 103: ...fig TDP via PECI RdPkgConfig Core Count RdPCIConfigLocal DTS PECI commands will also support DTS temperature data readings Please see Section 2 5 7 DTS Temperature Data for PECI command details Also r...

Страница 104: ...ch frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements 6 The 150W TDP SKU is intended for the dual processor workstation...

Страница 105: ...tation of this Thermal Profile should result in virtually no TCC activation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for system and en...

Страница 106: ...4600 Product Families Thermal Mechanical Design Guide for system and environmental implementation details Table 5 3 8 Core 150W Thermal Profile Workstation Platform SKU Only Power W Maximum TCASE C M...

Страница 107: ...on 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design tar...

Страница 108: ...l profile 3 Implementation of this Thermal Profile should result in virtually no TCC activation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Gui...

Страница 109: ...easured at maximum TCASE 3 These specifications are based on final silicon characterization 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered under multi...

Страница 110: ...ide for system and environmental implementation details Notes 1 Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP 2 Please refer to Table...

Страница 111: ...mal Mechanical Design Guide for system and environmental implementation details Figure 5 7 DTS 6 Core 130W Thermal Profile 1U Table 5 7 8 6 Core 130W Thermal Profile Table 1U Sheet 1 of 2 Power W Maxi...

Страница 112: ...maximum TCASE 3 These specifications are based on final silicon characterization 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered under multiple VIDs fo...

Страница 113: ...ted to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP 2 This Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 5 9 for discre...

Страница 114: ...can dissipate TDP is measured at maximum TCASE 3 These specifications are based on final silicon characterization 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may b...

Страница 115: ...no TCC activation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for system and environmental implementation details Notes 1 Some processor...

Страница 116: ...e TDP is measured at maximum TCASE 3 These specifications are based on final silicon characterization 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered u...

Страница 117: ...de for system and environmental implementation details Notes 1 Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP 2 Please refer to Table...

Страница 118: ...5 4600 Product Families Thermal Mechanical Design Guide for system and environmental implementation details Figure 5 14 DTS 6 Core 95W Thermal Profile 1U Table 5 13 8 6 Core 95W Thermal Profile Table...

Страница 119: ...found in Table 7 3 The processor may be delivered under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency r...

Страница 120: ...his Thermal Profile should result in virtually no TCC activation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for system and environmental...

Страница 121: ...e based on final silicon characterization 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered under multiple VIDs for each frequency 5 FMB or Flexible Moth...

Страница 122: ...entation of this Thermal Profile should result in virtually no TCC activation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for system and...

Страница 123: ...4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target...

Страница 124: ...le 3 Implementation of this Thermal Profile should result in virtually no TCC activation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for...

Страница 125: ...ate TDP is measured at maximum TCASE 3 These specifications are based on final silicon characterization 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered...

Страница 126: ...r discrete points that constitute this thermal profile 2 Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for system and environmental impleme...

Страница 127: ...Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC Please refer to the electrical loadline spec...

Страница 128: ...Table 7 3 The processor may be delivered under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requiremen...

Страница 129: ...cifications in Section 7 8 1 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at ma...

Страница 130: ...de for system and environmental implementation details Notes 1 Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP 2 Please refer to Table...

Страница 131: ...ctivation Refer to the Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide for system and environmental implementation details Figure 5 27 DTS 2 Core 80W Ther...

Страница 132: ...profile is required for any temperatures exceeding Tcontrol 5 1 4 1 8 Core LV95W Thermal Specifications Notes 1 These values are specified at VCC_MAX for all processor frequencies Systems must be des...

Страница 133: ...for system and environmental implementation details 3 The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance 4 The Sh...

Страница 134: ...res up to Tcontrol is permitted at all power levels 4 The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to exceed 96 hours per inst...

Страница 135: ...n simulations which will be updated as further characterization data becomes available 4 Power specifications are defined at all VIDs found in Table 7 3 The processor may be delivered under multiple V...

Страница 136: ...metrically constrained platform Please refer to Table 5 28 for discrete points that constitute the thermal profile 2 Implementation of this Thermal Profile should result in virtually no TCC activation...

Страница 137: ...n Processor E5 1600 E5 2600 E5 4600 Product Families Thermal Mechanical Design Guide Notes 1 Figure is not to scale and is for reference only 2 B1 Max 52 57 mm Min 52 43 mm 3 B2 Max 45 07 mm Min 44 93...

Страница 138: ...ing the internal processor core clocks The processor intelligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method The Adaptive Thermal Mo...

Страница 139: ...w core operating voltage by issuing a new SVID code to the VCC voltage regulator The voltage regulator must support dynamic SVID steps to support this method During the voltage change it will be neces...

Страница 140: ...dulation is programmable via bits 3 0 of the same IA32_CLOCK_MODULATION MSR In On Demand mode the duty cycle can be programmed from 6 25 on 93 75 off to 93 75 on 6 25 off in 6 25 increments On Demand...

Страница 141: ...vation is independent of processor activity and does not generate any Intel QuickPath Interconnect transactions If THERMTRIP_N is asserted all processor supplies VCC VTTA VTTD VSA VCCPLL VCCD must be...

Страница 142: ...us is the default value The input sense assertion time recognized by the processor is programmable 1 us is the default value If the sense assertion time is programmed to zero then the processor ignor...

Страница 143: ...d and address DDR 0 1 2 3 _DQ 63 00 Data Bus DDR3 Data bits DDR 0 1 2 3 _DQS_DP 17 00 DDR 0 1 2 3 _DQS_DN 17 00 Data strobes Differential pair Data ECC Strobe Differential strobes latch data ECC for e...

Страница 144: ...system memory reads DDR_VREFDQRX_C01 is used for memory channels 0 and 1 while DDR_VREFDQRX_C23 is used for memory channels 2 and 3 DDR_VREFDQTX_C01 DDR_VREFDQTX_C23 Voltage reference for system memo...

Страница 145: ...s Miscellaneous Signals Sheet 1 of 2 Signal Name Description PE_RBIAS This input is used to control PCI Express bias currents A 50 ohm 1 tolerance resistor must be connected from this land to VSS by t...

Страница 146: ...ck differential input The Intel QPI forward clock frequency is half the Intel QPI data rate QPI 0 1 _CLKTX_DN DP Reference Clock Differential Output These pins provide the PLL reference clock differen...

Страница 147: ...and TAP Signals Signal Name Description BPM_N 7 0 Breakpoint and Performance Monitor Signals I O signals from the processor that indicate the status of breakpoints and programmable counters used for...

Страница 148: ...essors Since this is an I O land external agents are allowed to assert this land which will cause the processor to take a machine check exception This signal is sampled after PWRGOOD assertion On the...

Страница 149: ...r details SAFE_MODE_BOOT Safe mode boot Strap SAFE_MODE_BOOT allows the processor to wake up safely by disabling all clock gating this allows BIOS to load registers or patches if required This signal...

Страница 150: ...his signal is also used by the VCCPLL and VTT rails to switch their output voltage to support future processors SKTOCC_N SKTOCC_N Socket occupied is used to indicate that a processor is present This i...

Страница 151: ...as VCCD Note The processor must be provided VCCD_01 and VCCD_23 for proper operation even in configurations where no memory is populated A VRM EVRD 12 0 controller is recommended but not required VCC...

Страница 152: ...Signal Descriptions 152 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

Страница 153: ...emory interface utilizes DDR3 technology which consists of numerous signal groups These include Reference Clocks Command Signals Control Signals and Data Signals Each group consists of numerous signal...

Страница 154: ...by VTTD The set of DC electrical specifications shown in Table 7 17 is used with devices normally operating from a VTTD interface supply 7 1 5 1 Input Device Hysteresis The PECI client and host input...

Страница 155: ...rocessor E5 1600 E5 2600 E5 4600 Product Families BSDL Boundary Scan Description Language for more details A translation buffer should be used to connect to the rest of the chain unless one of the oth...

Страница 156: ...can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default...

Страница 157: ...e supply to the voltage regulator is stable 7 1 9 3 2 SetVID Fast Command The SetVID fast command contains the target VID in the payload byte The range of voltage is defined in the VID table The VR sh...

Страница 158: ...ulation For example typical power states are 00h run in normal mode a command of 01h shed phases mode and an 02h pulse skip The VR may reduce the number of active phases from PS0 to PS1 or PS0 to PS2...

Страница 159: ...500 9D 1 03000 C0 1 20500 E3 1 38000 35 0 51000 58 0 68500 7B 0 86000 9E 1 03500 C1 1 21000 E4 1 38500 36 0 51500 59 0 69000 7C 0 86500 9F 1 04000 C2 1 21500 E5 1 39000 37 0 52000 5A 0 69500 7D 0 8700...

Страница 160: ...in the appropriate platform design guidelines 7 2 Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 7 5 The buffer type indicates which signaling...

Страница 161: ...C SSTL_15 Notes 1 Qualifier for a buffer type Table 7 5 Signal Groups Sheet 1 of 3 Differential Single Ended Buffer Type Signals1 DDR3 Reference Clocks2 Differential SSTL Output DDR 0 1 2 3 _CLK_D N P...

Страница 162: ...press Miscellaneous Signals Single ended Analog Input PE_RBIAS_SENSE Reference Input Output PE_RBIAS PE_VREF_CAP DMI2 PCI Express Signals Differential DMI2 Input DMI_RX_D N P 3 0 DMI2 Output DMI_TX_D...

Страница 163: ...v Input BIST_ENABLE BMCINIT FRMAGENT PWRGOOD PMSYNC RESET_N SAFE_MODE_BOOT SOCKET_ID 1 0 TXT_AGENT TXT_PLTEN Open Drain CMOS Input Output CAT_ERR_N CPU_ONLY_RESET MEM_HOT_C 01 23 _N PROCHOT_N Open Dra...

Страница 164: ...or FRB details see Section 7 4 The signal used to latch PROCHOT_N for enabling FRB mode is RESET_N 2 BIST_ENABLE is sampled at RESET_N de assertion and CPU_ONLY_RESET de assertion on the falling edge...

Страница 165: ...another entity can disable one or more specific processor cores 7 5 Mixing Processors Intel supports and validates and four two processor configurations only in which all processors operate with the s...

Страница 166: ...s may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with...

Страница 167: ...please refer to the processor case temperature specifications 2 These ratings apply to the Intel component and do not include the tray or packaging 3 Failure to adhere to this specification can affec...

Страница 168: ...8 DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature TCASE specified in Sec...

Страница 169: ...is not coupled in the scope probe 7 For the 8 6 core processor refer to Table 7 13 and corresponding Figure 7 3 For the 4 2 core processor refer to Table 7 14 and corresponding Figure 7 4 The processo...

Страница 170: ...responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please refer to the VR12 IMVP7 Pulse Width Modulation Specification for fu...

Страница 171: ...60 VID 0 033 VID 0 048 VID 0 063 1 2 3 4 5 6 65 VID 0 037 VID 0 052 VID 0 067 1 2 3 4 5 6 70 VID 0 041 VID 0 056 VID 0 071 1 2 3 4 5 6 75 VID 0 045 VID 0 060 VID 0 075 1 2 3 4 5 6 80 VID 0 049 VID 0 0...

Страница 172: ...core Icc ranges are as follows 0 185 A for 150 W processor 0 165 A for 135 W 130 W 115 W processors 0 135 A for 95 W LV95W 8C processors 0 100 A for 70 W LV70W 8C processors 0 85 A for 60 W processor...

Страница 173: ...W processor 0 135 A for 95 W processor 0 100 A for 80 W processor 60 VID 0 033 VID 0 048 VID 0 063 1 2 3 4 5 6 65 VID 0 037 VID 0 052 VID 0 067 1 2 3 4 5 6 70 VID 0 041 VID 0 056 VID 0 071 1 2 3 4 5 6...

Страница 174: ...lume One Figure 7 4 4 2 Core Processor VCC Static and Transient Tolerance Loadlines VID 0 020 VID 0 000 VID 0 020 VID 0 040 VID 0 060 VID 0 080 VID 0 100 VID 0 120 VID 0 140 VID 0 160 0 10 20 30 40 50...

Страница 175: ...mpacted by failing to meet durations specified in this graph Ensure that the platform design can handle peak and average current based on the specification 5 Processor or voltage regulator thermal pro...

Страница 176: ...all notes associated with each specification TOS_MAX Time duration of VCC overshoot above VccMAX value at the new lighter load 25 s 7 6 Figure 7 6 VCC Overshoot Example Waveform Table 7 15 VCC Oversho...

Страница 177: ...resistors are terminated to VSS 10 Input leakage current is specified for all DDR3 signals 11 DRAM_PWR_OK_C 01 23 must have a maximum of 30 ns rise or fall time over VCCD 0 55 300 mV and 200 mV and th...

Страница 178: ...ssing point must meet the absolute and relative crossing point specifications simultaneously 5 VHavg can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes 6 VCROSS is defi...

Страница 179: ...put Low Voltage RTEST 500 ohm 0 12 VTT V VOH Output High Voltage RTEST 500 ohm 0 88 VTT V RON Buffer On Resistance Signals BPM_N 7 0 TDO EAR_N 14 IIL Input Leakage Current Signals PREQ_N TCK TDI TMS T...

Страница 180: ...0 320 V 1 2 5 VIH_MIN Input High Voltage Signal PWRGOOD 0 640 V 1 2 5 VOL_CMOS1 05v Output Low Voltage 0 12 VTT V 1 2 VOH_CMOS1 05v Output High Voltage 0 88 VTT V 1 2 IIL_CMOS1 05v Input Leakage Curr...

Страница 181: ...for the PCI Express are available in the PCI Express Base Specification Revision 3 0 This document will provide only the processor exceptions to the PCI Express Base Specification Revision 3 0 7 8 3 2...

Страница 182: ...720 730 740 750 760 770 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 VHavg mV Crossing Point mV 550 mV 250 mV 250 0 5 VHavg 700 550 0 5 VHavg 700 0 0V VIH 150 mV VIL 150 mV...

Страница 183: ...and are only observable through simulation Therefore proper simulation is the only way to verify proper timing and signal quality 7 9 1 DDR3 Signal Quality Specifications Various scenarios for the DDR...

Страница 184: ...irection and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot undershoot Baseboard designs which meet signal integrity and timing requirements and w...

Страница 185: ...ot undershoot events even of lesser magnitude note that if AF 0 1 then the event occurs at all times and no other events can occur 7 9 5 4 Reading Overshoot Undershoot Specification Tables The oversho...

Страница 186: ...undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 0 1 specifications If all of these worst case overshoot or undershoot events meet the...

Страница 187: ...CW41 ODCMOS I O DDR_SDA_C23 R43 ODCMOS I O DDR_VREFDQRX_C01 BY16 DC I DDR_VREFDQRX_C23 J1 DC I DDR_VREFDQTX_C01 CN41 DC O DDR_VREFDQTX_C23 P42 DC O DDR0_BA 0 CM28 SSTL O DDR0_BA 1 CN27 SSTL O DDR0_BA...

Страница 188: ...DQ 52 CC37 SSTL I O Table 8 1 Land Name Sheet 3 of 49 Land Name Land No Buffer Type Direction DDR0_DQ 53 CE37 SSTL I O DDR0_DQ 54 CC41 SSTL I O DDR0_DQ 55 CB42 SSTL I O DDR0_DQ 56 CH38 SSTL I O DDR0_D...

Страница 189: ...STL O DDR01_RCOMP 0 CA17 Analog I DDR01_RCOMP 1 CC19 Analog I DDR01_RCOMP 2 CB20 Analog I Table 8 1 Land Name Sheet 5 of 49 Land Name Land No Buffer Type Direction DDR1_BA 0 DB26 SSTL O DDR1_BA 1 DC25...

Страница 190: ...55 CV40 SSTL I O Table 8 1 Land Name Sheet 7 of 49 Land Name Land No Buffer Type Direction DDR1_DQ 56 DE37 SSTL I O DDR1_DQ 57 DF38 SSTL I O DDR1_DQ 58 DD40 SSTL I O DDR1_DQ 59 DB40 SSTL I O DDR1_DQ 6...

Страница 191: ...DR2_CAS_N T16 SSTL O DDR2_CKE 0 AA25 SSTL O DDR2_CKE 1 T26 SSTL O Table 8 1 Land Name Sheet 9 of 49 Land Name Land No Buffer Type Direction DDR2_CKE 2 U27 SSTL O DDR2_CKE 3 AD24 SSTL O DDR2_CKE 4 AE25...

Страница 192: ...O Table 8 1 Land Name Sheet 11 of 49 Land Name Land No Buffer Type Direction DDR2_DQ 62 AF2 SSTL I O DDR2_DQ 63 AE3 SSTL I O DDR2_DQS_DN 00 T38 SSTL I O DDR2_DQS_DN 01 AD38 SSTL I O DDR2_DQS_DN 02 W31...

Страница 193: ...2 J25 SSTL O DDR3_CKE 3 N25 SSTL O DDR3_CKE 4 R25 SSTL O Table 8 1 Land Name Sheet 13 of 49 Land Name Land No Buffer Type Direction DDR3_CKE 5 R27 SSTL O DDR3_CLK_DN 0 J23 SSTL O DDR3_CLK_DN 1 J21 SST...

Страница 194: ...L I O Table 8 1 Land Name Sheet 15 of 49 Land Name Land No Buffer Type Direction DDR3_DQS_DN 01 L37 SSTL I O DDR3_DQS_DN 02 G33 SSTL I O DDR3_DQS_DN 03 P28 SSTL I O DDR3_DQS_DN 04 B10 SSTL I O DDR3_DQ...

Страница 195: ..._TX_DP 2 B44 PCIEX O Table 8 1 Land Name Sheet 17 of 49 Land Name Land No Buffer Type Direction DMI_TX_DP 3 C45 PCIEX O TXT_PLTEN V52 CMOS I DRAM_PWR_OK_C01 CW17 CMOS1 5v I DRAM_PWR_OK_C23 L15 CMOS1 5...

Страница 196: ...57 PCIEX3 I PE2C_RX_DN 8 AK56 PCIEX3 I PE2C_RX_DN 9 AM58 PCIEX3 I Table 8 1 Land Name Sheet 19 of 49 Land Name Land No Buffer Type Direction PE2C_RX_DP 10 AJ57 PCIEX3 I PE2C_RX_DP 11 AR57 PCIEX3 I PE2...

Страница 197: ...I PE3D_RX_DP 12 AG47 PCIEX3 I PE3D_RX_DP 13 AN47 PCIEX3 I PE3D_RX_DP 14 AM46 PCIEX3 I PE3D_RX_DP 15 AN45 PCIEX3 I Table 8 1 Land Name Sheet 21 of 49 Land Name Land No Buffer Type Direction PE3D_TX_DN...

Страница 198: ...I O QPI0_DTX_DN 18 CG51 QPI O QPI0_DTX_DN 19 CG49 QPI O QPI0_DTX_DP 00 BV50 QPI O Table 8 1 Land Name Sheet 23 of 49 Land Name Land No Buffer Type Direction QPI0_DTX_DP 01 BV52 QPI O QPI0_DTX_DP 02 BU...

Страница 199: ...QPI1_DTX_DN 11 CW45 QPI O QPI1_DTX_DN 12 DC47 QPI O QPI1_DTX_DN 13 DD46 QPI O QPI1_DTX_DN 14 CV44 QPI O QPI1_DTX_DN 15 DC45 QPI O QPI1_DTX_DN 16 DD44 QPI O QPI1_DTX_DN 17 CW43 QPI O QPI1_DTX_DN 18 DC4...

Страница 200: ...7 of 49 Land Name Land No Buffer Type Direction RSVD K58 RSVD M48 RSVD W15 RSVD Y48 SAFE_MODE_BOOT DA55 CMOS I SKTOCC_N BU49 O SOCKET_ID 0 CY52 CMOS I SOCKET_ID 1 BC49 CMOS I SVIDALERT_N CR43 CMOS I S...

Страница 201: ...14 PWR VCC AV16 PWR VCC AV2 PWR VCC AV4 PWR VCC AV6 PWR VCC AV8 PWR VCC AW1 PWR Table 8 1 Land Name Sheet 29 of 49 Land Name Land No Buffer Type Direction VCC AW11 PWR VCC AW13 PWR VCC AW15 PWR VCC AW...

Страница 202: ...2 PWR VCC BK14 PWR VCC BK16 PWR VCC BK2 PWR VCC BK4 PWR VCC BK6 PWR VCC BK8 PWR Table 8 1 Land Name Sheet 31 of 49 Land Name Land No Buffer Type Direction VCC BN1 PWR VCC BN11 PWR VCC BN13 PWR VCC BN1...

Страница 203: ...CCD_01 CW23 PWR VCCD_01 CW25 PWR VCCD_01 CW27 PWR VCCD_01 DD18 PWR Table 8 1 Land Name Sheet 33 of 49 Land Name Land No Buffer Type Direction VCCD_01 DD20 PWR VCCD_01 DD22 PWR VCCD_01 DD24 PWR VCCD_01...

Страница 204: ...AB6 GND VSS AC31 GND VSS AC9 GND VSS AD26 GND VSS AD34 GND VSS AD36 GND Table 8 1 Land Name Sheet 35 of 49 Land Name Land No Buffer Type Direction VSS AD42 GND VSS AD44 GND VSS AD46 GND VSS AD48 GND V...

Страница 205: ...GND VSS AT8 GND VSS AU45 GND VSS AU47 GND VSS AU49 GND VSS AU51 GND VSS AV42 GND Table 8 1 Land Name Sheet 37 of 49 Land Name Land No Buffer Type Direction VSS AV54 GND VSS AV56 GND VSS AW55 GND VSS...

Страница 206: ...50 GND VSS BT52 GND VSS BT54 GND VSS BT56 GND VSS BU45 GND VSS BU51 GND VSS BW1 GND Table 8 1 Land Name Sheet 39 of 49 Land Name Land No Buffer Type Direction VSS BW11 GND VSS BW13 GND VSS BW15 GND VS...

Страница 207: ...GND VSS CH48 GND VSS CH50 GND VSS CH52 GND VSS CH54 GND VSS CH6 GND VSS CJ11 GND Table 8 1 Land Name Sheet 41 of 49 Land Name Land No Buffer Type Direction VSS CJ17 GND VSS CJ29 GND VSS CJ3 GND VSS C...

Страница 208: ...13 GND VSS CW15 GND VSS CW29 GND VSS CW31 GND VSS CW33 GND VSS CW35 GND VSS CW37 GND Table 8 1 Land Name Sheet 43 of 49 Land Name Land No Buffer Type Direction VSS CW39 GND VSS CW5 GND VSS CW51 GND VS...

Страница 209: ...GND VSS G5 GND VSS G51 GND VSS G53 GND VSS G57 GND VSS G9 GND VSS H10 GND VSS H12 GND Table 8 1 Land Name Sheet 45 of 49 Land Name Land No Buffer Type Direction VSS H14 GND VSS H32 GND VSS H34 GND VSS...

Страница 210: ...V50 GND VSS V8 GND VSS W13 GND VSS W33 GND Table 8 1 Land Name Sheet 47 of 49 Land Name Land No Buffer Type Direction VSS W37 GND VSS W41 GND VSS W43 GND VSS W45 GND VSS W47 GND VSS W5 GND VSS W51 GND...

Страница 211: ...ssor Land Listing VTTD AY42 PWR VTTD BD42 PWR VTTD BH42 PWR VTTD BK56 PWR VTTD BL51 PWR VTTD BM42 PWR VTTD BR55 PWR VTTD BU47 PWR VTTD BV42 PWR VTTD BY20 PWR VTTD BY22 PWR VTTD CA21 PWR VTTD CA23 PWR...

Страница 212: ...I O AA39 VSS GND AA41 DDR2_DQ 13 SSTL I O AA43 PE3D_TX_DN 14 PCIEX3 O AA45 PE3D_TX_DP 12 PCIEX3 O AA47 PE3C_TX_DP 9 PCIEX3 O AA49 PE3A_RX_DP 3 PCIEX3 I AA5 VSS GND AA51 PE3B_RX_DP 7 PCIEX3 I AA53 PE3B...

Страница 213: ..._DQ 31 SSTL I O AD34 VSS GND AD36 VSS GND AD38 DDR2_DQS_DN 01 SSTL I O AD4 DDR2_DQS_DN 16 SSTL I O AD40 DDR2_DQ 09 SSTL I O AD42 VSS GND AD44 VSS GND AD46 VSS GND Table 8 2 Land Number Sheet 3 of 48 L...

Страница 214: ...PWR AG43 VSS GND AG45 PE3A_RX_DP 1 PCIEX3 I Table 8 2 Land Number Sheet 5 of 48 Land No Land Name Buffer Type Direction AG47 PE3D_RX_DP 12 PCIEX3 I AG49 PE3C_RX_DP 11 PCIEX3 I AG5 VSS GND AG51 PE3C_RX...

Страница 215: ...D PWR Table 8 2 Land Number Sheet 7 of 48 Land No Land Name Buffer Type Direction AM44 RSVD AM46 PE3D_RX_DP 14 PCIEX3 I AM48 VTTA PWR AM50 PE2A_TX_DP 1 PCIEX3 O AM52 PE2A_TX_DP 3 PCIEX3 O AM54 VTTA PW...

Страница 216: ...D AU1 VCC PWR AU11 VCC PWR AU13 VCC PWR AU15 VCC PWR AU17 VCC PWR AU3 VCC PWR Table 8 2 Land Number Sheet 9 of 48 Land No Land Name Buffer Type Direction AU43 BPM_N 2 ODCMOS I O AU45 VSS GND AU47 VSS...

Страница 217: ...I_TX_DP 0 PCIEX O B44 DMI_TX_DP 2 PCIEX O B46 RSVD B48 DMI_RX_DP 1 PCIEX I B50 DMI_RX_DP 3 PCIEX I B52 VSS GND B54 VSA PWR B6 VSS GND B8 VSS GND Table 8 2 Land Number Sheet 11 of 48 Land No Land Name...

Страница 218: ..._DP 03 QPI I BE57 QPI0_DRX_DP 08 QPI I BE7 VCC PWR Table 8 2 Land Number Sheet 13 of 48 Land No Land Name Buffer Type Direction BE9 VCC PWR BF10 VCC PWR BF12 VCC PWR BF14 VCC PWR BF16 VCC PWR BF2 VCC...

Страница 219: ...S GND BK52 VSS GND BK54 VSS GND BK56 VTTD PWR BK58 QPI0_CLKRX_DP QPI I Table 8 2 Land Number Sheet 15 of 48 Land No Land Name Buffer Type Direction BK6 VCC PWR BK8 VCC PWR BL1 VSS GND BL11 VSS GND BL1...

Страница 220: ...VD BR45 SVIDDATA ODCMOS I O BR47 RSVD BR49 QPI0_DRX_DP 18 QPI I BR5 VCC PWR BR51 QPI0_DRX_DN 15 QPI I BR53 VSS GND BR55 VTTD PWR Table 8 2 Land Number Sheet 17 of 48 Land No Land Name Buffer Type Dire...

Страница 221: ...CC_SENSE O BY20 VTTD PWR BY22 VTTD PWR BY24 VSS GND BY26 VCC PWR BY28 VCC PWR BY30 VCC PWR BY32 VCC PWR Table 8 2 Land Number Sheet 19 of 48 Land No Land Name Buffer Type Direction BY34 VCC PWR BY36 V...

Страница 222: ...CB34 DDR0_DQ 39 SSTL I O CB36 VSS GND Table 8 2 Land Number Sheet 21 of 48 Land No Land Name Buffer Type Direction CB38 DDR0_DQ 48 SSTL I O CB4 DDR0_DQ 09 SSTL I O CB40 DDR0_DQS_DN 06 SSTL I O CB42 D...

Страница 223: ...O CE33 DDR0_DQS_DN 04 SSTL I O CE35 DDR0_DQ 34 SSTL I O CE37 DDR0_DQ 53 SSTL I O CE39 DDR0_DQS_DN 15 SSTL I O CE41 DDR0_DQ 50 SSTL I O Table 8 2 Land Number Sheet 23 of 48 Land No Land Name Buffer Typ...

Страница 224: ...CH4 DDR0_DQ 10 SSTL I O CH40 DDR0_DQS_DN 07 SSTL I O CH42 DDR0_DQ 58 SSTL I O CH44 VSS GND CH46 VSS GND Table 8 2 Land Number Sheet 25 of 48 Land No Land Name Buffer Type Direction CH48 VSS GND CH50...

Страница 225: ...CL41 DDR0_DQ 63 SSTL I O CL43 VSS GND CL45 QPI1_DRX_DP 19 QPI I CL47 QPI1_DRX_DP 17 QPI I CL49 QPI1_DRX_DN 15 QPI I CL5 VSS GND CL51 QPI1_DRX_DN 13 QPI I Table 8 2 Land Number Sheet 27 of 48 Land No...

Страница 226: ...et 29 of 48 Land No Land Name Buffer Type Direction CP56 VSS GND CP58 QPI1_DRX_DP 06 QPI I CP6 DDR1_DQ 20 SSTL I O CP8 DDR1_DQS_DP 11 SSTL I O CR1 DDR1_DQS_DN 09 SSTL I O CR11 VSS GND CR13 DDR1_DQ 24...

Страница 227: ...06 SSTL I O CU41 DDR1_DQ 51 SSTL I O CU43 QPI1_DTX_DP 17 QPI O CU45 QPI1_DTX_DP 11 QPI O CU47 QPI1_DTX_DP 05 QPI O CU49 QPI1_DTX_DP 02 QPI O Table 8 2 Land Number Sheet 31 of 48 Land No Land Name Buff...

Страница 228: ...SSTL I O CY4 DDR1_DQ 03 SSTL I O CY40 VSS GND CY42 DDR_SCL_C01 ODCMOS I O Table 8 2 Land Number Sheet 33 of 48 Land No Land Name Buffer Type Direction CY44 VSS GND CY46 RSVD CY48 RSVD CY50 VSS GND CY5...

Страница 229: ...DB42 QPI1_DTX_DP 19 QPI O DB44 QPI1_DTX_DP 16 QPI O Table 8 2 Land Number Sheet 35 of 48 Land No Land Name Buffer Type Direction DB46 QPI1_DTX_DP 13 QPI O DB48 QPI1_DTX_DP 10 QPI O DB50 QPI1_DTX_DN 07...

Страница 230: ...DDR1_DQ 15 SSTL I O DF12 VSS GND DF14 DDR1_ECC 1 SSTL I O DF16 DDR1_ECC 7 SSTL I O DF18 DDR1_BA 2 SSTL O DF20 DDR1_MA 07 SSTL O Table 8 2 Land Number Sheet 37 of 48 Land No Land Name Buffer Type Direc...

Страница 231: ...G21 DDR3_PAR_ERR_N SSTL I G23 DDR3_MA 09 SSTL O G25 VSS GND G27 DDR3_DQS_DN 08 SSTL I O G29 DDR3_ECC 0 SSTL I O G3 DDR3_DQ 56 SSTL I O Table 8 2 Land Number Sheet 39 of 48 Land No Land Name Buffer Ty...

Страница 232: ...DDR3_CLK_DN 3 SSTL O K24 DDR3_CKE 0 SSTL O Table 8 2 Land Number Sheet 41 of 48 Land No Land Name Buffer Type Direction K26 VSS GND K28 VSS GND K30 VSS GND K32 DDR3_DQ 29 SSTL I O K34 VSS GND K36 DDR3...

Страница 233: ...1 DDR3_DQS_DP 05 SSTL I O N13 VSS GND N15 VCCD_23 PWR N17 VCCD_23 PWR N19 VCCD_23 PWR N21 VCCD_23 PWR N23 VCCD_23 PWR Table 8 2 Land Number Sheet 43 of 48 Land No Land Name Buffer Type Direction N25 D...

Страница 234: ...8 VSS GND Table 8 2 Land Number Sheet 45 of 48 Land No Land Name Buffer Type Direction T30 DDR2_DQ 23 SSTL I O T32 DDR2_DQS_DN 11 SSTL I O T34 DDR2_DQ 20 SSTL I O T36 DDR2_DQ 03 SSTL I O T38 DDR2_DQS_...

Страница 235: ...4 SSTL O W27 DDR2_ECC 6 SSTL I O W29 DDR2_DQ 18 SSTL I O W3 DDR2_DQ 56 SSTL I O W31 DDR2_DQS_DN 02 SSTL I O W33 VSS GND Table 8 2 Land Number Sheet 47 of 48 Land No Land Name Buffer Type Direction W35...

Страница 236: ...Processor Land Listing 236 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

Страница 237: ...0 E5 4600 Product Families Thermal Mechanical Design Guide for complete details on the LGA2011 0 land FCLGA10 socket The package components shown in Figure 9 1 include the following 1 Integrated Heat...

Страница 238: ...lume One 5 Reference datums 6 All drawing dimensions are in millimeters mm 7 Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is...

Страница 239: ...Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families 239 Datasheet Volume One Package Mechanical Specifications Figure 9 2 Processor Package Drawing Sheet 1 of 2...

Страница 240: ...Package Mechanical Specifications 240 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One Figure 9 3 Processor Package Drawing Sheet 2 of 2...

Страница 241: ...r IHS 2 This is the maximum static force that can be applied by the heatsink and Independent Loading Mechanism ILM 3 These specifications are based on limited testing for design characterization Loadi...

Страница 242: ...igure 9 4 shows the topside markings on the processor This diagram is to aid in the identification of the processor Notes 1 XXXXX Country of Origin 2 SPEED Format X XX GHz and no rounding Table 9 3 Pr...

Страница 243: ...wer in 1U or 2U chassis with appropriate ducting Check with Blade manufacturer for compatibility Boxed Intel Thermal Solution STS200PNRW Order Code BXSTS200PNRW A 25 5 mm Tall Passive Heat Sink Soluti...

Страница 244: ...the PWM and PECI interface along with Digital Thermal Sensors DTS 10 1 3 Intel Thermal Solution STS200P and STS200PNRW Boxed 25 5 mm Tall Passive Heat Sink Solutions The STS200P and STS200PNRW are av...

Страница 245: ...boxed thermal solutions will be sold separately Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling Baseboard keepout zones are Figure 10 4 Figure 10 7 Phy...

Страница 246: ...ED IN MILLIMETERS AND DEFINE ZONES THEY HAVE NO TOLERANCES ASSOCIATED WITH THEM 3 SOCKET KEEP OUT DIMENSIONS SHOWN FOR REFERNCE ONLY 4 MAXIMUM OUTLINE OF SOCKET MUST BE PLACED SYMMETRIC TO THE ILM HOL...

Страница 247: ...G11950 2 B DWG NO SHT REV THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFIED WITHOUT...

Страница 248: ...SCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION SHEET 3 OF 4 DO NOT SCALE DRAWING SCALE 1 000 PTMI B...

Страница 249: ...SED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION SHEET 4 OF 4 DO NOT SCALE DRAWING SCALE 1 500 PTMI B G11...

Страница 250: ...3 29 10 B ROLLED PART TO 002 CHANGED SPRING CUP GEOMETRY TO FIT DELRIN SPACER 7 21 10 THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION IT IS DISCLOSED IN CONFIDENCE AND ITS CONT ENTS...

Страница 251: ...G NO SHT REV THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION IT IS DISCLOSED IN CONFIDENCE AND ITS CONT ENTS MAY NOT BE DISCLOSED REPRODUCED DI SPLAYED OR MODIFIED WITHOUT THE PRI OR...

Страница 252: ...0 E5 4600 Product Families Datasheet Volume One Figure 10 10 4 Pin Fan Cable Connector For Active Heat Sink The drawing contains intel corporation information Its contents may not be reproduced displa...

Страница 253: ...et Volume One Boxed Processor Specifications Figure 10 11 4 Pin Base Baseboard Fan Header For Active Heat Sink The drawing contains intel corporation information Its contents may not be reproduced dis...

Страница 254: ...resent approximately 8 inch pounds of torque More than that may damage the retention mechanism components 10 3 Fan Power Supply STS200C The 4 pin PWM controlled thermal solution is being offered to he...

Страница 255: ...r and thermal solution boundary conditions such as Psica TLA airflow flow impedance etc see Table 10 2 and Table 10 3 It is recommended that the ambient air temperature outside of the chassis be kept...

Страница 256: ...200C without fan 0 180 61 6 26 0 14 91 5x91 5x64 130W Pedestal 6 and 8 Core STS200C with fan 0 180 61 6 Max RPM N A 91 5x91 5x64 115W Pedestal 8 Core STS200P 0 241 52 2 16 0 406 91 5x91 5x25 5 115W Pe...

Страница 257: ...Volume One Boxed Processor Specifications Boxed Processor Intel Xeon processor E5 2600 product family Installation and warranty manual Intel Inside Logo Boxed Thermal Solution Thermal solution assemb...

Страница 258: ...Boxed Processor Specifications 258 Intel Xeon Processor E5 1600 E5 2600 E5 4600 Product Families Datasheet Volume One...

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