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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
2.5.2.6
Package Configuration Capabilities
Table 2-6
combines both read and write services. Any service listed as a “read” would
use the RdPkgConfig() command and a service listed as a “write” would use the
WrPkgConfig() command. PECI requests for memory temperature or other data
generated outside the processor package do not trigger special polling cycles on the
processor memory or SMBus interfaces to procure the required information.
2.5.2.6.1
DRAM Thermal and Power Optimization Capabilities
DRAM thermal and power optimization (also known as RAPL or “Running Average
Power Limit”) services provide a way for platform thermal management solutions to
program and access DRAM power, energy and temperature parameters. Memory
temperature information is typically used to regulate fan speeds, tune refresh rates and
throttle the memory subsystem as appropriate. Memory temperature data may be
derived from a variety of sources including on-die or on-board DIMM sensors, DRAM
activity information or a combination of the two. Though memory temperature data is a
byte long, range of actual temperature values are determined by the DIMM
specifications and operating range.
Note:
DRAM related PECI services described in this section apply only to the memory
connected to the specific processor PECI client in question and not the overall platform
memory in general. For estimating DRAM thermal information in closed loop throttling
mode, a dedicated SMBus is required between the CPU and the DIMMs. The processor
PCU requires access to the VR12 voltage regulator for reading average output current
information through the SVID bus for initial DRAM RAPL related power tuning.
Table 2-6
provides a summary of the DRAM power and thermal optimization capabilities
that can be accessed over PECI on the processor.
The Index values referenced in
Table 2-6
are in decimal format.
Table 2-6
also provides information on alternate inband mechanisms to access similar
or equivalent information through register reads and writes where applicable. The user
should consult the
Intel® 64 and IA-32 Architectures Software Developer’s Manual
(SDM) Volumes 1, 2, and 3
or
Intel® Xeon® Processor E5 Product Family Datasheet
Volume Two
for details on MSR and CSR register contents.
CC: 0x80
Response timeout. The processor was not able to generate the required response in a
timely fashion. Retry is appropriate.
CC: 0x81
Response timeout. The processor is not able to allocate resources for servicing this
command at this time. Retry is appropriate.
CC: 0x90
Unknown/Invalid/Illegal Request
CC: 0x91
PECI control hardware, firmware or associated logic error. The processor is unable to
process the request.
Table 2-5.
WrPkgConfig() Response Definition (Sheet 2 of 2)
Response
Meaning
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