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UPI-C42/UPI-L42

SYNC MODE TIMING DIAGRAMS

290414 – 15

Minimum Specifications

SYNC Operation Time, t

SYNC

e

3.5 XTAL 2 Clock cycles. Reset Time, t

RS

e

4 t

CY

.

NOTE:

The rising and falling edges of T0 should occur during low state of XTAL 2 clock.

APPLICATIONS

290414 – 12

Figure 7. UPI-C42 Keyboard Controller

290414 – 9

Figure 8. 8088-UPI-C42 Interface

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Содержание UPI-C42

Страница 1: ...d Most Other Microprocessor Families Y Interchangeable ROM and OTP EPROM Versions Y Expandable I O Y Sync Mode Available Y Over 90 Instructions 70 Single Byte Y Quick Pulse Programming Algorithm Ð Fast OTP Programming Y Available in 40 Lead Plastic 44 Lead Plastic Leaded Chip Carrier and 44 Lead Quad Flat Pack Packages See Packaging Spec Order Ý240800 Package Type P N and S The UPI C42 is an enhan...

Страница 2: ... Sync Mode by applying 12 5V to it CS 6 7 24 I CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EA 7 8 25 I EXTERNAL ACCESS External access input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused RD 8 9 26 I READ I O read input which enables the master CPU to read data and status words fro...

Страница 3: ...interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full OBF interrupt P25 as Input Buffer Full IBF interrupt P26 as DMA Request DRQ and P27 as DMA ACKnowledge DACK PROG 25 28 43 I O PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 This ...

Страница 4: ... 2 style mouse support 82L42PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portable apps 87L42 N P S 4K One Time Programmable Version N e 44 lead PLCC P e 40 lead PDIP S e 44 lead QFP D e 40 lead CERDIP KBC e Key Board Control SCC e Scan Code Control THE INTEL 82C42 As shown in the UPI C42 product matrix the UPI C42 is offered as a pre programmed 80C42 with var ious versions of MultiKey 42...

Страница 5: ...ins on Reset If the EN FLAGS instruction has been execut ed P24 becomes the OBF Output Buffer Full pin A 1 written to P24 enables the OBF pin the pin outputs the OBF Status Bit A 0 written to P24 disables the OBF pin the pin remains low This pin can be used to indicate that valid data is available from the UPI in Output Data Bus Buff er If EN FLAGS has been executed P25 be comes the IBF Input Buff...

Страница 6: ... the range of branch instructions beyond their normal 2K range and at the same time prevents the user from inadvertently crossing the 2K boundary PROGRAM MEMORY BANK SWITCH The switching of 2K program memory banks is ac complished by directly setting or resetting the most significant bit of the program counter bit 11 see Figure 5 Bit 11 is not altered by normal increment ing of the program counter...

Страница 7: ... D1h 0 n Clear A20 Sequence 0 W DDh 0 0 1 W FFh 0 n 1 W D1h 0 n Double Trigger Set 1 W D1h 0 n Sequence 0 W DFh 0 1 1 W FFh 0 n 1 W D1h 0 n Invalid Sequence 1 W XXh 3 1 n No Change in State 0 W DDh 1 n of A20 Bit NOTES 1 Indicates that P2 1 remains at the previous logic level 2 Only FFh commands in a valid A20 sequence have no effect on IBF An FFh issued at any other time will activate IBF 3 Any c...

Страница 8: ...t necessary to the user who does not wish to take advantage of any new C42 function ality The C42 will be completely compatible with all current NMOS code applications In order to use new features however some code modifications will be necessary All new instructions can easily be in serted into existing code by use of the ASM 48 mac ro facility as shown in the following example Macname MACRO DB 6...

Страница 9: ...ng pulse Each word is programmed com pletely before moving on to the next and is followed by a verification step The following is a list of the pins used for programming and a description of their functions Pin Function XTAL 2 Clock Input Reset Initialization and Address Latching Test 0 Selection of Program or Verify Mode EA Activation of Program Verify Signature Row Security Bit Modes BUS Address...

Страница 10: ...the UPI C42 OPT is also compatible with In tel s Inteligent Programming Algorithm which is used to program the NMOS UPI 42AH OTP devices The entire sequence of program pulses and byte verifications is performed at VCC e 6 25V and VDD e 12 75V When the inteligent Programming cycle has been completed all bytes should be com pared to the original data with VCC e 5 0 VDD e 5V Verify A verify should be...

Страница 11: ...ame It facilitates automatic device identification and will be present in the ROM and OTP ver sions Location 10H contains the manufacturer code For Intel it is 89H Location 11H contains the device code The code is 43H and 42H for the 8042AH 80C42 and OTP 8742AH 87C42 respectively The code is 44H for any device with the security bit set by Intel C User signatureÐThe user signature memory is impleme...

Страница 12: ...s Code Modes Port 2 Port 1 T0 RST SS EA PROG VDD VCC 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7 Programming 0 0 1 HV 1 VDDH VCC Address Addr a0 a1 X X X X X X Mode 0 1 1 HV STB VDDH VCC Data In Addr Verification 0 0 1 HV 1 VCC VCC Address Addr a0 a1 X X X X X X Mode 1 1 1 HV 1 VCC VCC Data Out Addr Sync Mode STB 0 HV 0 X VCC VCC X X X X X X X X X X X X X X X X X X X High Signature Prog 0 0 1 HV 1 VDD...

Страница 13: ...tions SYNC Operation Time tSYNC e 3 5 XTAL 2 Clock cycles Reset Time tRS e 4 tCY NOTE The rising and falling edges of T0 should occur during low state of XTAL 2 clock APPLICATIONS 290414 12 Figure 7 UPI C42 Keyboard Controller 290414 9 Figure 8 8088 UPI C42 Interface 13 ...

Страница 14: ...UPI C42 UPI L42 APPLICATIONS Continued 290414 10 Figure 9 8048H UPI C42 Interface 290414 11 Figure 10 UPI C42 8243 Keyboard Scanner 290414 13 Figure 11 UPI C42 80 Column Matrix Printer Interface 14 ...

Страница 15: ...8 V All Pins VIH Input High Voltage 2 0 VCC 2 0 VCC a 0 3 V Except XTAL2 RESET VIH1 Input High Voltage 3 5 VCC 2 0 VCC a 0 3 V XTAL2 RESET VOL Output Low Voltage D0 D7 0 45 0 45 V IOL e 2 0 mA UPI C42 IOL e 1 3 mA UPI L42 VOL1 Output Low Voltage 0 45 0 45 V IOL e 1 6 mA UPI C42 P10P17 P20P27 Sync IOL e 1 mA UPI L42 VOL2 Output Low Voltage PROG 0 45 0 45 V IOL e 1 0 mA UPI C42 IOL e 0 7 mA UPI L42 ...

Страница 16: ... DC CHARACTERISTICSÐPROGRAMMING UPI C42 AND UPI L42 TA e 25 C g5 C VCC e 6 25V g0 25V VDD e 12 75V g0 25V Symbol Parameter Min Max Units VDDH VDD Program Voltage High Level 12 5 13 V 1 VDDL VDD Voltage Low Level 4 75 5 25 V VPH PROG Program Voltage High Level 2 0 5 5 V VPL PROG Voltage Low Level b0 5 0 8 V VEAH Input High Voltage for EA 12 0 13 0 V 2 VEAL EA Voltage Low Level b0 5 5 25 V IDD VDD H...

Страница 17: ...ameter Min Max Units tAR CS A0 Setup to RDv 0 ns tRA CS A0 Hold After RDu 0 ns tRR RD Pulse Width 160 ns tAD CS A0 to Data Out Delay 130 ns tRD RDv to Data Out Delay 0 130 ns tDF RDu to Data Float Delay 85 ns DBB WRITE Symbol Parameter Min Max Units tAW CS A0 Setup to WRv 0 ns tWA CS A0 Hold After WRu 0 ns tWW WR Pulse Width 160 ns tDW Data Setup to WRu 130 ns tWD Data Hold After WRu 0 ns 17 ...

Страница 18: ...s tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data Valid 0 130 ns tCRQ RD or WR to DRQ Cleared 110 ns 1 NOTE 1 CL e 150 pF AC CHARACTERISTICS PORT 2 Symbol Parameter f tCY 3 Min Max Units tCP Port Control Setup Before Falling Edge of PROG 1 15 tCYb28 55 ns 1 tPC Port Control Hold After Falling Edge of PROG 1 10 tCY 125 ns 2 tPR PROG to Time P2 Input Must Be Valid 8 15 tCYb16...

Страница 19: ...05 ms tTW Test 0 Setup Time for Program Mode 4tCY tWT Test 0 Hold Time after Program Mode 4tCY tDO Test 0 to Data Out Delay 4tCY tWW RESET Pulse Width to Latch Address 4tCY tr tf PROG Rise and Fall Times 0 5 100 ms tCY CPU Operation Cycle Time 2 5 3 75 ms tRE RESET Setup Time before EAu 4tCY tOPW Overprogram Pulse Width 2 85 78 75 ms 1 tDE EA High to VDD High 1tCY NOTES 1 This variation is a funct...

Страница 20: ...rystal Series Resistance Should be Less Than 30X at 12 5 MHz XTAL1 Configuration Table XTAL1 Connection 1 to Ground 2 10 KX Resistor 3 Not Connected to Ground Not recommended for CHMOS Recommended configuration for Low power configuration designs Causes approximately designs which will use both recommended for CHMOS only 16 mA of additional current flow NMOS and CHMOS parts This designs to provide...

Страница 21: ...UPI C42 UPI L42 WAVEFORMS READ OPERATIONÐDATA BUS BUFFER REGISTER 290414 22 WRITE OPERATIONÐDATA BUS BUFFER REGISTER 290414 23 CLOCK TIMING 290414 24 21 ...

Страница 22: ...e D C Characteristics Table 3 When programming the 87C42 a 0 1 mF capacitor is required across VDD and ground to suppress spurious voltage transients which can damage the device VERIFY MODE 290414 26 NOTES 1 PROG must float if EA is low 2 PROG must float or e 5V when EA is high 3 P10 P17 e 5V or must float 4 P24 P27 e 5V or must float 5 A0 must be held low during programming verify modes 22 ...

Страница 23: ... DMA 290414 27 PORT 2 290414 28 PORT TIMING DURING EXTERNAL ACCESS EA 290414 29 On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync the Program Counter Contents are Available 23 ...

Страница 24: ...A A4 A7 to Bits 4 7 of 1 1 Status MOVD A Pp Input Expander 1 2 port to A MOVD Pp A Output A to 1 2 Expander port ANLD Pp A AND A to Expander 1 2 port ORLD Pp A OR A to Expander 1 2 port Mnemonic Description Bytes Cycles DATA MOVES MOV A Rr Move register to A 1 1 MOV A Rr Move data memory 1 1 to A MOV A Ýdata Move immediate to A 2 2 MOV Rr A Move A to register 1 1 MOV Rr A Move A to data 1 1 memory...

Страница 25: ...er 2 2 and jump JC addr Jump on Carry e 1 2 2 JNC addr Jump on Carry e 0 2 2 JZ addr Jump on A Zero 2 2 JNZ addr Jump on A not Zero 2 2 JT0 addr Jump on T0 e 1 2 2 JNT0 addr Jump on T0 e 0 2 2 JT1 addr Jump on T1 e 1 2 2 JNT1 addr Jump on T1 e 0 2 2 JF0 addr Jump on F0 Flag e 1 2 2 JF1 addr Jump on F1 Flag e 1 2 2 JTF addr Jump on Timer Flag 2 2 e 1 Clear Flag JNIBF addr Jump on IBF Flag 2 2 e 0 J...

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