Intel® Storage Server SSR212MC2
Feature Summary
Revision 1.2
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Figure 6: PMC* PM8388 Block Diagram
1.6.1 Embedded
Processor
The embedded RISC Processor is a MIPS Technologies* MIPS4K with an EJTAG debugging
interface.
It supports the SMP protocol and SES and is connected as a virtual port with the device base
SAS address. SMP commands are uploaded from Flash memory.
1.6.2
Memory Interface & Device Initialization
The PM8388 device has a 16-bit wide asynchronous memory interface. It is able to address 4
banks of Flash or SRAM of 2 Mbytes each. The memory banks can be 8-bit or 16-bit wide.
The Flash Memory Interface provides a way to configure device features during the reset
sequence. After system reset the processor loads an 8-Kbyte initialization string.
This initialization string contains information such as the SAS base address of the PM8388
device, identification of a subtractive port, per port configuration of the transmitter pre-emphasis
level, per port configuration of receiver equalization level, per port configuration of the transmit
swing, HDD spin-up delay values, HDD spin-up delay interval values, GPIO control and
manufacturer specific information.
