Intel
®
Server Board S5000VCL TPS
Appendix D: POST Code Diagnostic LED Decoder
Revision 2.3
Intel order number: D64569-007
57
Table 44. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
Checkpoint
MSB
LSB
Description
Host Processor
0x10h OFF OFF
OFF R Power-on
initialization of the host processor (bootstrap processor)
0x11h OFF OFF
OFF A Host
processor
cache initialization (including AP)
0x12h OFF OFF G R Starting
application processor initialization
0x13h OFF OFF G A SMM
initialization
Chipset
0x21h Off
Off
R G
Initializing a chipset component
Memory
0x22h Off
Off
A
Off
Reading
configuration data from memory (SPD on DIMM)
0x23h
Off
Off
A
G
Detecting presence of memory
0x24h
Off
G
R
Off
Programming timing parameters in the memory controller
0x25h
Off
G
R
G
Configuring memory parameters in the memory controller
0x26h Off G A
Off
Optimizing
memory controller settings
0x27h Off G A G
Initializing
memory, such as ECC init
0x28h G
Off
R
Off
Testing
memory
PCI Bus
0x50h
Off
R
Off
R
Enumerating PCI busses
0x51h Off R
Off
A
Allocating
resources to PCI busses
0x52h
Off
R
G
R
Hot Plug PCI controller initialization
0x53h
Off
R
G
A
Reserved for PCI bus
0x54h
Off
A
Off
R
Reserved for PCI bus
0x55h
Off
A
Off
A
Reserved for PCI bus
0x56h
Off
A
G
R
Reserved for PCI bus
0x57h
Off
A
G
A
Reserved for PCI bus
USB
0x58h
G
R
Off
R
Resetting USB bus
0x59h
G
R
Off
A
Reserved for USB devices
ATA/ATAPI/SATA
0x5Ah
G
R
G
R
Resetting PATA/SATA bus and all devices
0x5Bh
G
R
G
A
Reserved for ATA
SMBUS
0x5Ch G A
Off
R
Resetting
SMBUS
0x5Dh
G
A
Off
A
Reserved for SMBUS
Local Console
0x70h
Off
R
R
R
Resetting the video controller (VGA)
0x71h Off R R A
Disabling
the video controller (VGA)
0x72h Off R A R
Enabling
the video controller (VGA)
Remote Console
0x78h
G
R
R
R
Resetting the console controller
0x79h
G
R
R
A
Disabling the console controller
0x7Ah
G
R
A
R
Enabling the console controller