Power and Environmental Specifications
Intel
®
Server Board S5000VCL TPS
Revision
2.3
Intel order number: D64569-007
40
8.2.8
Dynamic Loading
The output voltages shall remain within limits for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50 Hz
and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The
step load may occur anywhere within the MIN load to the MAX load
conditions.
Table 35. Transient Load Requirements
Output
Step Load Size (See note 2)
Load Slew Rate
Test Capacitive Load
+3.3 V
6.0 A
0.25 A/
sec 250
F
+5 V
4.0 A
0.25 A/
sec 400
F
12 V
18.0 A
0.25 A/
sec 2200
F
1, 2
+5 VSB
0.5 A
0.25 A/
sec 20
F
Notes:
1. Step loads on each 12 V output may happen simultaneously.
2. The +12 V should be tested with 2200
F evenly split between the four +12 V rails.
8.2.9
Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive loading
ranges.
Table 36. Capacitive Loading Conditions
Output
Minimum
Maximum
Units
+3.3 V
250
6,800
F
+5 V
400
4,700
F
+12 V
500 each
11,000
F
-12 V
1
350
F
+5 VSB
20
350
F
8.2.10
Closed-Loop Stability
The power supply shall be unconditionally stable under all line/load/transient load conditions
including capacitive load ranges. A minimum of: 45 degrees phase margin and -10 dB gain
margin is required. The power supply manufacturer shall provide proof of the unit’s closed-loop
stability with local sensing through the submission of bode plots. Closed-loop stability must be
ensured at the maximum and minimum loads as applicable.
8.2.11
Common Mode Noise
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency
band of 10 Hz to 30 MHz.
