Intel
®
PXA27x Processor Developer’s Kit - User’s Guide
69
3.2.2.13
Scratch Registers1/2/3 (SCRATCH1/2/3)
These scratch registers are used for debugging. The values stored remain resident even during deep
sleep.
3.3
Processor Registers
Some of the Intel
®
PXA270 Processor registers require a specific configuration for use with the kit.
This section provides setup information for the following:
•
Section 3.3.1 — Memory-Control Registers
•
Section 3.3.2 — LCD-Control Registers
For complete details of these processor registers, see the corresponding chapter in the
Intel
®
PXA27x Processor Family Developer’s Manual
.
Note:
In the following tables, ‘X’ means that a bit’s setting does not matter (“don’t care”) for basic kit
system operation. Settings of these bits depend upon user software requirements.
3.3.1
Memory-Control Registers
The following subsections provide the recommended settings for the memory-control registers.
These settings are required for proper operation of the Intel
®
PXA270 Processor in a stand-alone
application
or
in combination with the main board. The following registers must be configured:
•
Section 3.3.1.1 — SDRAM Configuration Register (MDCNFG)
•
Section 3.3.1.2 — SDRAM Mode Register Set Configuration Register (MDMRS)
•
Section 3.3.1.3 — SLP SDRAM Mode Register Set Configuration Register (MDMRSLP)
•
Section 3.3.1.4 — SDRAM Memory Device Refresh Register (MDREFR)
•
Section 3.3.1.5 — Static Memory Control Register 0 (MSC0)
•
Section 3.3.1.6 — Static Memory Control Register 1 (MSC1)
•
Section 3.3.1.7 — Static Memory Control Register 2 (MSC2)
•
Section 3.3.1.8 — Expansion Memory Configuration Register (MECR)
Table 32. Scratch Register Bit Definitions
Physical Addresses:
0x0800_0010
0x0800 0110
0x0800 0120
Scratch
Intel
®
PXA27x Processor Developer’s Kit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Name
Scratch
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Access
Description
31:0
Scratch
R/W
Scratch register
