74
Intel
®
PXA27x Processor Developer’s Kit
- User’s Guide
3.3.1.6
Static Memory Control Register 1 (MSC1)
Static chip select nCS2 is logically split across two devices: the SRAM on the Intel
®
PXA270
Processor and the FPGA on the main board. The timing values shown in the following table are for
the slowest device — in this case, the SRAM.
MSC1 Recommended Settings:
3.3.1.7
Static Memory Control Register 2 (MSC2)
MSC2 Recommended Settings:
3.3.1.8
Expansion Memory Configuration Register (MECR)
MECR Recommended Settings:
C
C
D
1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Stand-alone Intel
®
PXA270 Processor
and
Intel
®
PXA270 Processor with main board
X
†
XXX
†
XXXX
†
XXXX
†
X
†
XXX
†
1
100
1100
1101
0
001
†
On the
kit
, the GPIO for nCS3 serves as the PCMCIA PSKTSEL signal. Thus, no memory is attached to nCS3.
B
8
8
4
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9
8
7
6
5
4
3
2
1
0
Stand-alone Intel
®
PXA270 Processor
X
1
XXX
1
XXXX
1
XXXX
1
X
1
XXX
1
X
XXX
XXXX
XXXX
X
XXX
Processor card with main board
X
1
XXX
1
XXXX
1
XXXX
1
X
1
XXX
1
1
0011
1000
1000
2
0
100
NOTES:
1. These values depend upon the expansion card connected to the system.
2. Worst case = read.
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9
8
7
6
5
4
3
2
1
0
Stand-alone Intel
®
PXA270 Processor
0X0
0
X
Processor card with main board
0X0
X
†
1
†
The state of this bit depends upon the presence or absence of an expansion card on the kit. For more information, see the
MECR register description in the Memory Controller chapter of the
Intel
®
PXA27x Processor Family Developer’s Manual
.
