76
Intel
®
PXA27x Processor Developer’s Kit
- User’s Guide
3.3.2
LCD-Control Registers
The following subsections provide the recommended settings for the Intel
®
PXA270 Processor
LCD-control registers. These settings are required for proper operation with the Toshiba
LTM035A776C – 3.5” QVGA panel.
The following registers must be configured:
•
Section 3.3.2.1 — LCD Controller Control Register 0 (LCCR0)
•
Section 3.3.2.2 — LCD Controller Control Register 1 (LCCR1)
•
Section 3.3.2.3 — LCD Controller Control Register 2 (LCCR2)
•
Section 3.3.2.4 — LCD Controller Control Register 3 (LCCR3)
•
Section 3.3.2.5 — LCD Controller Control Register 4 (LCCR4)
•
Section 3.3.2.6 — LCD Controller Control Register 5 (LCCR5)
The recommended settings
for the LCD-control registers presume the following:
•
Core is clocked off of the core PLL, with a core run-mode frequency of 130 MHz (L=10 in the
Core Clock Configuration Register)
•
The LCD-controller frequency is 65 MHz (see the Clocks and Power Manager chapter in the
Intel
®
PXA27x Processor Family Developer’s Manual
)
It may be necessary to adjust the recommended settings
, depending on the following:
•
Custom clock configurations:
— Clock sources
— Run- and turbo-mode frequencies
— Use of fast-bus mode
For clock-configuration information, see the Clocks and Power Manager chapter in the
Intel
®
PXA27x Processor Family Developer’s Manual
.
•
Presence of an alternate LCD
3.3.2.1
LCD Controller Control Register 0 (LCCR0)
LCCR0 Recommended Settings:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Toshiba LTM04C380K VGA
000 0000
1
1
0
1
1
0000 0000
1
0
0
0
1
1
1
1
0
0
0
1
Toshiba LTM035A776C QVGA
000 0000
1
1
0
1
1
0000 0000
1
0
0
0
1
1
1
1
0
0
0
1
