Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz—Package Mechanical Specifications and Pin
Information
Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz
DS
January 2007
36
Order Number: 315876-002
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is
an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TEST1
Input
TEST1 must have a stuffing option of separate pull down resistors to V
SS
.
TEST2
Input
TEST2 must have a 51W +/- 5% pull down resistor to V
SS
.
THERMDA
Other
Thermal Diode Anode.
THERMDC
Other
Thermal Diode Cathode.
THERMTRIP#
Output
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature
to ensure that there are no false trips. The processor stops all execution when
the junction temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of both FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset.
V
CC
Input
Processor core power supply.
V
CCA
Input
V
CCA
provides isolated power for the internal processor core PLLs
.
V
CCP
Input
Processor I/O Power Supply.
V
CCSENSE
Output
V
CCSENSE
is an isolated low impedance connection to processor core power
(V
CC
). It can be used to sense or measure power near the silicon with little
noise.
VID[5:0]
Output
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (V
CC
). Unlike some previous generations of processors, these
are CMOS signals driven by the Intel
®
Celeron
®
Processor 1.66 GHz/1.83 GHz.
The voltage supply for these pins must be valid before the VR can supply V
CC
to
the processor. Conversely, the VR output must be disabled until the voltage
supply for the VID pins becomes valid. The VID pins are needed to support the
processor voltage specification variations. Refer to
Table 4
for definitions of
these pins. The VR must supply the voltage that is requested by the pins, or
disable itself.
V
SSSENSE
Output
V
SSSENSE
is an isolated low impedance connection to processor core V
SS
. It can
be used to sense or measure ground near the silicon with little noise.
Table 11.
Signal Description (Sheet 7 of 7)
Name
Type
Description
