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Intel

Celeron

Processor 1.66 GHz/1.83 GHz

January 2007

Order Number: 315876-002

Low Power Features—Intel

Celeron

Processor 1.66 GHz/1.83 GHz

2.1.2.3

Stop Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state. During a snoop or interrupt transaction, the processor enters the Stop

Grant Snoop state. The processor stays in this state until the snoop on the FSB has

been serviced (whether by the processor or another agent on the FSB) or the interrupt

has been latched. After the snoop is serviced or the interrupt is latched, the processor

returns to the Stop-Grant state.

2.1.2.4

Sleep State

The Sleep state is a very low power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and has stopped most of internal clocks. The

Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state,

the processor enters the Sleep state upon the assertion of the SLP# signal. The SLP#

pin has a minimum assertion of one BCLK period. The SLP# pin should only be asserted

when the processor is in the Stop Grant state. For the Intel

Celeron

Processor 1.66

GHz/1.83 GHz, the SLP# pin may only be asserted the processor core is in the Stop-

Grant state. SLP# assertions while the processor is not in the Stop-Grant state are out

of specification and may results in illegal operation.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep

state causes unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state.

Any transition on an input signal before the processor has returned to Stop-Grant state

results in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor resets itself, ignoring the

transition through Stop-Grant state. If RESET# is driven active while the processor is in

the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after

RESET# is asserted to ensure the processor correctly executes the reset sequence.

When the processor is in Sleep state, it does not respond to interrupts or snoop

transactions.

2.2

Enhanced Intel

SpeedStep

Technology (EIST)

Intel

Celeron

Processor 1.66 GHz/1.83 GHz does not support this feature.

2.3

Extended Halt State (C1E)

The Intel

Celeron

Processor 1.66 GHz/1.83 GHz Extended Halt State (C1E) enables

significant power savings. Extended HALT state is a low power state entered when the

processor core has executed the HALT or MWAIT instructions and Extended HALT state

has been enabled via the BIOS. When the processor core executes the HALT

instruction, the core is halted. The Extended HALT state is a lower power state than the

HALT state or Stop Grant state.

Note:

The Extended HALT (C1E) state must be enabled for the processor to remain within its

specifications.

The Extended HALT state requires support for dynamic VID transitions in the platform.

The processor automatically transitions to a lower core frequency and voltage operating

point before entering the Extended HALT state. Note that the processor FSB frequency

Содержание Pga478 - P4-2ghz 512kb 400mhz Fsb

Страница 1: ...Order Number 315876 002 Intel Celeron Processor 1 66 GHz 1 83 GHz Datasheet January 2007...

Страница 2: ...measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details The I...

Страница 3: ...and Pin Information 25 4 1 Package Mechanical Specifications 25 4 2 Processor Pin Out and Pin List 28 5 0 Thermal Specifications and Design Considerations 61 5 1 Thermal Specifications 62 Figures 1 Pa...

Страница 4: ...ad Pumped Signal Groups 32 13 DINV 3 0 Assignment To Data Bus 32 14 Alphabetical Signal Listing 37 15 Alphabetical Pin Listing 49 16 Power Specifications for the Intel Celeron Processor 1 66 GHz 1 83...

Страница 5: ...2007 DS Order Number 315876 002 5 Revision History Intel Celeron Processor 1 66 GHz 1 83 GHz Revision History Date Revision Description November 2006 001 Initial public release January 2007 002 Added...

Страница 6: ...Intel Celeron Processor 1 66 GHz 1 83 GHz maintains support for MMXTM Technology and Streaming SIMD instructions and full compatibility with IA32 software The on die 32 kB Level 1 instruction and dat...

Страница 7: ...d can thus help improve the overall security of the system Refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information Note The term AGTL is used to refer...

Страница 8: ...tp www intel com design intarch specupdt 311392 htm Intel E7520 Memory Controller Hub MCH Datasheet ftp download intel com design chipsets datashts 30300602 pdf Intel 6300ESB I O Controller Datasheet...

Страница 9: ...66 GHz 1 83 GHz 1 3 State of Data The data contained within this document represents the most accurate information available by the publication date Note All references to the Intel Celeron Processor...

Страница 10: ...z 1 83 GHz Intel Celeron Processor 1 66 GHz 1 83 GHz implements two software interfaces for requesting low power states the I O mapped ACPI P_BLK register block and the C state extension to the MWAIT...

Страница 11: ...to either Normal Mode or the AutoHALT Power Down state Refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals in Volume 3A 3B System Programming Guide for more information The sys...

Страница 12: ...should not be driven allowing the level to return to VCCP for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the...

Страница 13: ...ansactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the system bus while the processor is in Sleep state Any transition o...

Страница 14: ...te the processor first switches to the lower bus to core frequency ratio and then transition to the lower voltage VID While in the Extended HALT C1E state the processor processes bus snoops The proces...

Страница 15: ...and Ground Pins For clean on chip power distribution the Intel Celeron Processor 1 66 GHz 1 83 GHz has a large number of VCC power and VSS ground inputs All power pins must be connected to VCC power...

Страница 16: ...VRD 11 0 Design Guidelines for Embedded Implementations Supporting PGA478 The Intel Celeron Processor 1 66 GHz 1 83 GHz uses six voltage identification pins VID 5 0 to support automatic selection of p...

Страница 17: ...1 1 2500 0 1 1 1 1 0 1 2375 0 1 1 1 1 1 1 2250 1 0 0 0 0 0 1 2125 1 0 0 0 0 1 1 2000 1 0 0 0 1 0 1 1875 1 0 0 0 1 1 1 1750 1 0 0 1 0 0 1 1625 1 0 0 1 0 1 1 1500 1 0 0 1 1 0 1 1375 1 0 0 1 1 1 1 1250 1...

Страница 18: ...ignal including each other can result in component malfunction or incompatibility with future processors See Table 15 for a pin listing of the processor and the location of all RSVD pins For reliable...

Страница 19: ...ve at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous Table 5 FSB Pin Groups Signal Group Type Signals1 AGTL Common Clock Input Sy...

Страница 20: ...66 GHz 1 83 GHz and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequency Mode HFM and Lowest Frequency Mode LFM refer to the h...

Страница 21: ...processor should be as specified in the load lines in Figure 3 Adherence to load line specifications is required to ensure reliable processor operation Note that this differs from the VID employed by...

Страница 22: ...xperience excursions above VCCP However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Refer to processor I O Buffer Models for I V c...

Страница 23: ...etween 0V and VCCP Measured when the driver is tristated 7 Cpad1 includes die capacitance only for PWRGOOD No package parasitics are included 8 Cpad2 includes die capacitance for all other CMOS input...

Страница 24: ...igh Voltage 1 0 1 05 1 10 V 3 VOL Output Low Voltage 0 0 20 V IOL Output Low Current 11 4 50 mA 2 ILEAK Leakage Current 200 A 4 Cpad Pad Capacitance 1 8 2 3 2 75 pF 5 Notes 1 Unless otherwise noted al...

Страница 25: ...z 4 0 Package Mechanical Specifications and Pin Information 4 1 Package Mechanical Specifications The Intel Celeron Processor 1 66 GHz 1 83 GHz is available in 478 pin Micro FCPGA Micro Flip Chip PGA...

Страница 26: ...cal Specifications and Pin Information Intel Celeron Processor 1 66 GHz 1 83 GHz DS January 2007 26 Order Number 315876 002 Note All dimensions are in millimeters inches Values shown for reference onl...

Страница 27: ...Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep o...

Страница 28: ...here are additional load limitations against transient bend shock and tensile loading These limitations are more platform specific and should be obtained by contacting your field support Moreover the...

Страница 29: ...SS VSS 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 11 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VC...

Страница 30: ...alid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A...

Страница 31: ...re breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 s...

Страница 32: ...oth FSB agents DEFER Input DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memo...

Страница 33: ...Developer s Manuals in Volume 3A 3B System Programming Guide and the Intel Processor Identification and CPUID Instruction application note AP 485 application note FORCEPR Input The FORCEPR input can...

Страница 34: ...the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both FSB agents For a locked sequenc...

Страница 35: ...he specified setup time before RESET is deasserted There is a 55 ohm nominal on die pull up resistor on this signal RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent respo...

Страница 36: ...o false trips The processor stops all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin TMS Input TMS Test Mode Sele...

Страница 37: ...nc Input Output A 23 V3 Source Sync Input Output A 24 U3 Source Sync Input Output A 25 V2 Source Sync Input Output A 26 AA3 Source Sync Input Output A 27 AB2 Source Sync Input Output A 28 W2 Source Sy...

Страница 38: ...ync Input Output D 1 C22 Source Sync Input Output D 10 H22 Source Sync Input Output D 11 J22 Source Sync Input Output D 12 K23 Source Sync Input Output D 13 H23 Source Sync Input Output D 14 L23 Sourc...

Страница 39: ...t D 45 Y25 Source Sync Input Output D 46 AB25 Source Sync Input Output D 47 AA24 Source Sync Input Output D 48 U22 Source Sync Input Output D 49 T22 Source Sync Input Output D 5 G21 Source Sync Input...

Страница 40: ...TBN 3 V21 Source Sync Input Output DSTBP 0 K21 Source Sync Input Output DSTBP 1 N21 Source Sync Input Output DSTBP 2 T21 Source Sync Input Output DSTBP 3 W21 Source Sync Input Output FERR B5 Open Drai...

Страница 41: ...Reserved RSVD D7 Reserved RSVD R24 Reserved RSVD AE25 Reserved RSVD D1 Reserved RSVD C1 Reserved RSVD B2 Reserved RSVD C3 Reserved SKTOCC AE1 Power Other Output SLP C7 CMOS Input SMI E5 CMOS Input STP...

Страница 42: ...AC15 Power Other VCC AD15 Power Other VCC AE15 Power Other VCC AF15 Power Other VCC AA13 Power Other VCC AB14 Power Other VCC AC13 Power Other VCC AD14 Power Other VCC AE13 Power Other VCC AF14 Power...

Страница 43: ...r VCC C17 Power Other VCC C18 Power Other VCC D17 Power Other VCC D18 Power Other VCC E17 Power Other VCC E18 Power Other VCC F17 Power Other VCC F18 Power Other VCC A15 Power Other VCC B15 Power Othe...

Страница 44: ...7 Power Other VCCA A23 Power Other VCCP AC23 Power Other VCCP U6 Power Other VCCP AF25 Power Other VCCP AF26 Power Other VCCP AF23 Power Other VCCP AB21 Power Other VCCP AC22 Power Other VCCP AD21 Pow...

Страница 45: ...AD19 Power Other VSS AE19 Power Other VSS AF19 Power Other VSS AA16 Power Other VSS AB16 Power Other VSS AC16 Power Other VSS AD16 Power Other VSS AE16 Power Other VSS AF16 Power Other VSS AA14 Power...

Страница 46: ...Power Other VSS F5 Power Other VSS G6 Power Other VSS J5 Power Other VSS K6 Power Other VSS M5 Power Other VSS N6 Power Other VSS P5 Power Other VSS T6 Power Other VSS U5 Power Other VSS W6 Power Othe...

Страница 47: ...C23 Power Other VSS E24 Power Other VSS F23 Power Other VSS B21 Power Other VSS D22 Power Other VSS E21 Power Other VSS A19 Power Other VSS B19 Power Other VSS C19 Power Other VSS D19 Power Other VSS...

Страница 48: ...ower Other VSS N25 Power Other VSS R25 Power Other VSS T26 Power Other VSS V25 Power Other VSS W26 Power Other VSS H24 Power Other VSS J23 Power Other VSS L24 Power Other VSS M23 Power Other VSS P24 P...

Страница 49: ...ower Other A11 VSS Power Other A12 VCC Power Other A13 VCC Power Other A14 VSS Power Other A15 VCC Power Other A16 VSS Power Other A17 VCC Power Other A18 VCC Power Other A19 VSS Power Other A20 VCC P...

Страница 50: ...Source Sync Input Output AB3 VSS Power Other AB4 TDO Open Drain Output AB5 TMS CMOS Input AB6 VSS Power Other AB7 VSSSENSE Power Other Output AB8 VSS Power Other AB9 VCC Power Other AB10 VCC Power Ot...

Страница 51: ...ower Other AC18 VCC Power Other AC19 VSS Power Other AC20 VCC Power Other AC21 VSS Power Other AC22 VCCP Power Other AC23 VCCP Power Other AC24 VSS Power Other AC25 D 57 Source Sync Input Output AC26...

Страница 52: ...t AE4 VID 0 CMOS Output AE5 BPM 3 Common Clock Input Output AE6 VSS Power Other AE7 VCC Power Other AE8 VSS Power Other AE9 VCC Power Other AE10 VCC Power Other AE11 VSS Power Other AE12 VCC Power Oth...

Страница 53: ...Other AF18 VCC Power Other AF19 VSS Power Other AF20 VCC Power Other AF21 VSS Power Other AF22 VCCP Power Other AF23 VCCP Power Other AF24 VSS Power Other AF25 VCCP Power Other AF26 VCCP Power Other B...

Страница 54: ...VSS Power Other C9 VCC Power Other C10 VCC Power Other C11 VSS Power Other C12 VCC Power Other C13 VCC Power Other C14 VSS Power Other C15 VCC Power Other C16 VSS Power Other C17 VCC Power Other C18...

Страница 55: ...t D22 VSS Power Other D23 D 7 Source Sync Input Output D24 D 17 Source Sync Input Output D25 VSS Power Other D26 D 16 Source Sync Input Output E1 VSS Power Other E2 RS 1 Common Clock Input E3 HIT Comm...

Страница 56: ...ther F10 VCC Power Other F11 VSS Power Other F12 VCC Power Other F13 VSS Power Other F14 VCC Power Other F15 VCC Power Other F16 VSS Power Other F17 VCC Power Other F18 VCC Power Other F19 VSS Power O...

Страница 57: ...tput J1 A 4 Source Sync Input Output J2 VSS Power Other J3 REQ 3 Source Sync Input Output J4 HITM Common Clock Input Output J5 VSS Power Other J6 DEFER Common Clock Input J21 DSTBN 0 Source Sync Input...

Страница 58: ...Power Other M6 ADSTB 0 Source Sync Input Output M21 DSTBN 1 Source Sync Input Output M22 D 24 Source Sync Input Output M23 VSS Power Other M24 DP 3 Common Clock Input Output M25 DP 1 Common Clock Inp...

Страница 59: ...D 37 Source Sync Input Output R24 RSVD Reserved R25 VSS Power Other R26 COMP 1 Power Other Input Output T1 A 10 Source Sync Input Output T2 A 13 Source Sync Input Output T3 VSS Power Other T4 A 19 Sou...

Страница 60: ...nc Input Output W1 A 30 Source Sync Input Output W2 A 28 Source Sync Input Output W3 VSS Power Other W4 AP 1 Common Clock Input Output W5 BINIT Common Clock Input Output W6 VSS Power Other W21 DSTBP 3...

Страница 61: ...stem processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature TJ specifications at the corresponding thermal design power TDP v...

Страница 62: ...ariations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the TJ temperature can c...

Страница 63: ...measured ideality of the diode and ntrim is the diode ideality assumed by the temperature sensing device Table 17 Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA B22 Th...

Страница 64: ...s the TCC is not user configurable Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active A thermal...

Страница 65: ...demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On demand mode may be used at the same time automatic mode is enabled however if the system t...

Страница 66: ...When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism activates The DTS and TM1 TM2 temperature may not correspond to the thermal...

Страница 67: ...current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of the FORCEPR does not automatically assert PROCHOT As mentioned previously the PROC...

Страница 68: ...Intel Celeron Processor 1 66 GHz 1 83 GHz Thermal Specifications and Design Considerations Intel Celeron Processor 1 66 GHz 1 83 GHz DS January 2007 68 Order Number 315876 002...

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