User’s Manual
i945G2-IQNAR User’s Manual
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2.5
Advanced Chipset Features
By choosing the “Advanced Chipset Features” option from the “Initial Setup Screen” menu,
the screen below will be displayed. This sample screen contains the manufacturer’s default
values for the i945G2-IQNAR, as shown in Figure 2-4:
Figure 2.4: Advanced chipset features screen
Note:
DRAM default timings have been carefully chosen and should ONLY be
changed if data is being lost. Please first contact technical sup- port.
2.5.1 DRAM Timing Selectable
This item allows you to control the DRAM speed. The selections are “Manual” or “By SPD”.
2.5.2 CAS Latency Time
When DRAM Timing Selectable is set to [Manual], this field is adjustable. This controls the
CAS latency, which determines the time interval between SDRAM starting a read command
and receiving it. The options are [3T], [4T], [5T], and [Auto].
2.5.3 DRAM RAS# to CAS# Delay
When DRAM Timing selectable is set to [Manual], this field is adjust- able. When DRAM is
refreshed, the rows and columns are addressed separately. This setup item allows user to
determine the timing of the transition from RAS (row address strobe) to CAS (column
address strobe). The less the clock cycles are, the faster the DRAM speed is. Set- ting
options are [2T] to [5T], and [Auto].
