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Specification Update

AAU27.

Disabling Thermal Monitor While Processor is Hot, Then Re-enabling,

May Result in Stuck Core Operating Ratio

Problem:

If a processor is at its TCC (Thermal Control Circuit) activation temperature and then
Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a
subsequent re-enable of Thermal Monitor will result in an artificial ceiling on the
maximum core P-state. The ceiling is based on the core frequency at the time of
Thermal Monitor disable. This condition will only correct itself once the processor
reaches its TCC activation temperature again.

Implication:

Since Intel requires that Thermal Monitor be enabled in order to be operating within
specification, this erratum should never be seen during normal operation.

Workaround:

Software should not disable Thermal Monitor during processor operation.

Status:

For the steppings affected, see the Summary Tables of Changes.

AAU28.

Writing the Local Vector Table (LVT) when an Interrupt is Pending

May Cause an Unexpected Interrupt

Problem:

If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.

Implication:

An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service
Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.

Workaround:

Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.

Status:

For the steppings affected, see the Summary Tables of Changes.

AAU29.

xAPIC Timer May Decrement Too Quickly Following an Automatic

Reload While in Periodic Mode

Problem:

When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.

Implication:

When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.

Workaround:

None identified.

Status:

For the steppings affected, see the Summary Tables of Changes.

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Содержание G6950

Страница 1: ...Reference Number 322911 013 Intel Core i5 600 i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update January 2011 ...

Страница 2: ...r a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology Intel Virtualization Technology Intel VT x and Intel Virtualization Technology for Directed I O Intel VT d...

Страница 3: ...3 Specification Update Contents Revision History 5 Preface 6 Summary Tables of Changes 8 Identification Information 14 Errata 17 Specification Changes 49 Specification Clarifications 50 Documentation Changes 51 ...

Страница 4: ...Contents 4 Specification Update ...

Страница 5: ...cation table to include the SKU information for the Intel Core i5 655K and i3 550 processor June 2010 008 Added Errata AAU98 AAU102 July 2010 009 Erratum AAU32 added to this product Specification Update in error all erratum details removed from the specification update document August 2010 010 Updated Processor Identification table to include the SKU information for the Intel Core i3 560 processor...

Страница 6: ... Intel Pentium Processor G6950 Datasheet Volume 2 322910 002 Document Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Ref...

Страница 7: ...e of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of ...

Страница 8: ...s Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this document Status Doc Document change or update will be implemented Plan Fix This erratum may be fixed in a future steppi...

Страница 9: ...GP for Instructions Greater than 15 Bytes May be Preempted AAU13 X X No Fix General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit AAU14 X X No Fix LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode AAU15 X X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error AAU16 X X No Fix Debu...

Страница 10: ...ing an Interrupt Service Routine AAU37 X X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM AAU38 X X No Fix APIC Error Received Illegal Vector May be Lost AAU39 X X No Fix DR6 May Contain Incorrect Information When the First Instruction After a MOV SS r m or POP SS is a Store AAU40 X X No Fix An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a Syste...

Страница 11: ...cessor AAU64 X X No Fix LBR BTM or BTS Records May have Incorrect Branch From Information After an EIST Transition T states C1E or Adaptive Thermal Throttling AAU65 X X No Fix VMX Preemption Timer Does Not Count Down at the Rate Specified AAU66 X X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 AAU67 X X No Fix VM Exits Due to LIDT LGDT SIDT SGDT Do Not ...

Страница 12: ...ynamically Switch From 5 0GT s to 2 5GT s AAU90 X X No Fix PCI Express Cards May Not Train to x16 Link Width AAU91 X X No Fix Unexpected Graphics VID Transition During Warm Reset May Cause the System to Hang AAU92 X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Lost AAU93 X Fixed VM Entry to 64 Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different AAU94 X Fixed VM Entry Loadi...

Страница 13: ...st State Area of the VMCS AAU108 X No Fix Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior AAU109 X Fixed Execution of VMPTRLD May Corrupt Memory If Current VMCS Pointer is Invalid AAU110 X X No Fix PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Specification Changes Number SPECIFICATION CHANGES None for this revision of this spe...

Страница 14: ...l field of the Device ID register accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of that model See Table 1 for the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Number and Stepping ID value in the EAX registe...

Страница 15: ...ore 3 73 1 core 3 86 4 1 3 4 5 6 7 8 10 SLBLT i5 670 C 2 20652h 3 46 1333 733 2 core 3 60 1 core 3 73 4 1 3 4 5 6 7 8 10 SLBNE i5 661 C 2 20652h 3 33 1333 900 2 core 3 46 1 core 3 60 4 3 5 7 8 9 10 SLBLV i5 660 C 2 20652h 3 33 1333 733 2 core 3 46 1 core 3 60 4 1 3 4 5 6 7 8 10 SLBXL i5 655K K 0 20655h 3 20 1333 733 2 core 3 33 1 core 3 46 4 1 3 4 5 6 7 8 10 SLBLK i5 650 C 2 20652h 3 20 1333 733 2...

Страница 16: ...SE4 2 enabled 9 This processor has TDP of 87 W 10 The core frequency reported in the processor brand string is rounded to 2 decimal digits For example core frequency of 3 4666 repeating 6 is reported as 3 47 in brand string Core frequency of 3 3333 is reported as 3 33 in brand string SLBLR i3 530 C 2 20652h 2 93 1333 733 N A 4 1 3 5 8 10 SLBMS G6950 C 2 20652h 2 80 1066 533 N A 3 1 5 10 SLBT6 G696...

Страница 17: ...ng Operations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross page boundaries from WB WC memory types to UC WP WT memory types may start using an incorrect data size or may observe memory ordering violations Implication Upon crossing the page boundary the following...

Страница 18: ...xpected values Implication Performance Monitoring counter SIMD_INST_RETIRED may report count higher than expected Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAU5 Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem If any of the below circumstances occur it is possible that the load portion of the instruction will...

Страница 19: ...mmary Tables of Changes AAU7 Incorrect Address Computed for Last Byte of FXSAVE FXRSTOR Image Leads to Partial Memory Update Problem A partial memory state save of the 512 byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16 bit mode or if a memory address exceeds the 4GB limit while the...

Страница 20: ... s Manual Vol 1 Basic Architecture for information on the usage of the ENTER instructions This erratum is not expected to occur in Ring 3 Faults are usually processed in Ring 0 and stack switch occurs when transferring to Ring 0 Intel has not observed this erratum on any commercially available software Workaround None identified Status For the steppings affected see the Summary Tables of Changes A...

Страница 21: ...he Summary Tables of Changes AAU14 LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode Problem An exception interrupt event should be transparent to the LBR Last Branch Record BTS Branch Trace Store and BTM Branch Trace Message mechanisms However during a specific boundary condition where the exception interrupt occurs right after the execution of an instructio...

Страница 22: ...Real Mode to Protected Mode Problem During the transition from real mode to protected mode if an SMI System Management Interrupt occurs between the MOV to CR0 that sets PE Protection Enable bit 0 and the first FAR JMP the subsequent RSM Resume from System Management Mode may cause the lower two bits of CS segment register to be corrupted Implication The corruption of the bottom two bits of the CS ...

Страница 23: ... segment registers The value of the count may be inaccurate Implication The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or lower than the actual number of events Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAU22 GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Co...

Страница 24: ...ignaling created by this erratum Status For the steppings affected see the Summary Tables of Changes AAU25 IA32_MPERF Counter Stops Counting During On Demand TM1 Problem According to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide the ratio of IA32_MPERF MSR E7H to IA32_APERF MSR E8H should reflect actual performance while TM1 or on demand thrott...

Страница 25: ... the new vector when a LVT entry is written even if the new LVT entry has the mask bit set If there is no Interrupt Service Routine ISR set up for that vector the system will GP fault If the ISR does not do an End of Interrupt EOI the bit for the vector will be left set in the in service register and mask all interrupts at the same or lower priority Workaround Any vector programmed into an LVT ent...

Страница 26: ...cated at physical addresses that are mapped to WB memory type by the MTRRs Status For the steppings affected see the Summary Tables of Changes AAU31 Changing the Memory Type for an In Use Page Translation May Lead to Memory Ordering Violations Problem Under complex microarchitectural conditions if software changes the memory type for data being actively used and shared by multiple threads without ...

Страница 27: ...Mode Interrupt is Received while All Cores in C6 Problem If all logical processors in a core are in C6 an ExtINT delivery mode interrupt is pending in the xAPIC and interrupts are blocked with EFLAGS IF 0 the interrupt will be processed after C6 wakeup and after interrupts are re enabled EFLAGS IF 1 However the pending interrupt event will not be cleared Implication Due to this erratum an infinite...

Страница 28: ...ment Mode Due to this erratum if 1 A performance counter overflowed before an SMI 2 A PEBS record has not yet been generated because another count of the event has not occurred 3 The monitored event occurs during SMM then a PEBS record will be saved after the next RSM instruction When FREEZE_WHILE_SMM is set a PEBS should not be generated until the event occurs outside of SMM Implication A PEBS re...

Страница 29: ...rectable errors logged in IA32_CR_MC2_STATUS MSR 409H may also result in a system hang causing an Internal Timer Error MCACOD 0x0400h to be logged in another machine check bank IA32_MCi_STATUS Implication Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang and an Internal Timer Error to be logged Workaround None identified Status For the steppings affected see the Sum...

Страница 30: ...es of Changes AAU45 Performance Monitor Event EPT EPDPE_MISS May be Counted While EPT is Disable Problem Performance monitor event EPT EPDPE_MISS Event 4FH Umask 08H is used to count Page Directory Pointer table misses while EPT extended page tables is enabled Due to this erratum the processor will count Page Directory Pointer table misses regardless of whether EPT is enabled or not Implication Du...

Страница 31: ...alues and must be enabled in IA32_PERF_GLOBAL_CTRL MSR 38FH bits 3 0 All three values must be written to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counters Note that the performance counter will not increment when its IA32_PERFEVTSELx MSR has a value of 0x4300D2 0x4300B1 or 0x4300B5 because those values have a zero UMASK field bits 15 8 Status For the st...

Страница 32: ...ortion of the saved EFLAGS value then system software should perform a synchronized paging structure modification and TLB invalidation Status For the steppings affected see the Summary Tables of Changes AAU50 Back to Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS MSCOD Problem When back to back uncorrected machine check errors occur that would both be logged in the IA32_MC3_ST...

Страница 33: ...is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AAU54 APIC Timer CCR May Report 0 in Periodic Mode Problem In periodic mode the APIC timer CCR current count register is supposed to be automatically reloaded from the initial count register when the count reaches 0 consequently software would never be able to obser...

Страница 34: ...lly reported after INIT SIPI sequences and when waking up RLP s from the SENTER sleep state using the GETSEC WAKEUP command Implication An INIT SIPI sequence may show a non zero value in EAX upon wakeup when a zero value is expected RLP s waking up for the SENTER sleep state using the GETSEC WAKEUP command may show a different value in EAX upon wakeup than before going into the SENTER sleep state ...

Страница 35: ... self refresh entry are not critical there is no measurable impact due to this erratum Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAU61 VM Exits Due to EPT Violations Do Not Record Information About Pre IRET NMI Blocking Problem With certain settings of the VM execution controls VM exits due to EPT violations set bit 12 of the exit qualification ...

Страница 36: ...er an EIST Enhanced Intel SpeedStep Technology transition T states C1E C1 Enhanced or Adaptive Thermal Throttling Implication When the LBRs BTM or BTS are enabled some records may have incorrect branch From addresses for the first branch after an EIST transition T states C1E or Adaptive Thermal Throttling Workaround None identified Status For the steppings affected see the Summary Tables of Change...

Страница 37: ...h a 32 bit operand bit 11 of the VM exit instruction information field should be set to 1 Due to this erratum this bit is instead cleared to 0 indicating a 16 bit operand Implication Virtual machine monitors cannot rely on bit 11 of the VM exit instruction information field to determine the operand size of the instruction causing the VM exit Workaround Virtual Machine Monitor software may decode t...

Страница 38: ...after the last FP instruction a FP to MMX transition may not be counted Implication The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active Intel has not observed this erratum with any commercially available software Workaround None identified Sta...

Страница 39: ...se proximity on both channels in a mirrored channel pair No uncorrectable ECC or parity error will be logged in the machine check banks Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAU74 MSR_TURBO_RATIO_LIMIT MSR May Return Intel Turbo Boost Technology Core Ratio Multipliers for Non Existent Core Configurations Problem MSR_TURBO_RATIO_LIMIT MSR 1AD...

Страница 40: ...one identified Status For the steppings affected see the Summary Tables of Changes AAU78 If the APIC timer Divide Configuration Register Offset 03E0H is written at the same time that the APIC timer Current Count Register Offset 0390H reads 1H it is possible that the APIC timer will deliver two interrupts Problem If the APIC timer Divide Configuration Register Offset 03E0H is written at the same ti...

Страница 41: ...ing Problem The APIC Timer Current Counter Register may prematurely read 0x00000000 while the timer is still running This problem occurs when a core frequency or C state transition occurs while the APIC timer countdown is in progress Implication Due to this erratum certain software may incorrectly assess that the APIC timer countdown is complete when it is actually still running This erratum does ...

Страница 42: ...nly be terminated by a processor reset Intel has not observed this erratum with any commercially available software Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAU86 Processor Hangs on Package C6 State Exit Problem An internal timing condition in the processor power management logic will result in processor hangs upon a Package C6 state exit Impli...

Страница 43: ...wn The link will recover and re train to the L0 state however any outstanding packets queued during the speed change may be lost Implication Due to this erratum the link may lose sync resulting in link down with queued packet being lost No known failures have been observed on systems using production PCI Express graphics cards This erratum has only been observed in a synthetic test environment Wor...

Страница 44: ...he Summary Tables of Changes AAU94 VM Entry Loading an Unusable SS Might Not Set SS B to 1 Problem If the unusable bit bit 16 is 1 in the guest SS Stack Segment access rights field VM entry should set the B bit default stack pointer size in the SS stack segment register to 1 Due to this erratum VM entry may instead load SS B from bit 14 of the guest SS access rights field potentially clearing SS B...

Страница 45: ...e processor not to meet the JEDEC DDR3 DRAM specification requirement Section 4 17 4 Power Down clarifications Case 3 Implication Due to this erratum the processor may not meet the JEDEC DDR3 DRAM specification requirement that states CKE cannot be registered low twice within a tRFC min window Intel has not observed any functional failure due to this erratum Workaround None identified Status For t...

Страница 46: ...tion correctly Such operations include the VMREAD and VMWRITE instructions as well as VM entries and VM exits Implication If CR0 CD is set on either logical processor in a core the VMWRITE instruction may not correctly update the VMCS and the VMREAD instruction may not return correct data VM entries may not load state properly and may not establish VMX controls properly VM exits may not save or lo...

Страница 47: ...he integrated graphics engine continuously generates a large stream of writes to system memory and Intel Flex Memory Technology is enabled with a different amount of memory in each channel the memory arbiter may temporarily stop servicing other device initiated traffic In some cases this can cause certain USB devices such as keyboard and mouse to become unresponsive Intel has only observed this er...

Страница 48: ...id as expected A subsequent execution of the VMPTRLD Load Pointer to Virtual Machine Control Structure instruction may erroneously overwrite the four bytes at physical address 0000008FH Implication Due to this erratum the four bytes in system memory at physical address 0000008FH may be corrupted Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAU110 P...

Страница 49: ... 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volum...

Страница 50: ...al Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Man...

Страница 51: ... N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation Note Documentation changes for Intel 64 and IA 32 Architecture Software Developer s Manual ...

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