44
Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU92.
IO_SMI Indication in SMRAM State Save Area May Be Lost
Problem:
The IO_SMI bit (bit 0) in the IO state field at SMRAM offset 7FA4H is set to "1" by the
processor to indicate a System Management Interrupt (SMI) is either taken
immediately after a successful I/O instruction or is taken after a successful iteration of
a REP I/O instruction. Due to this erratum, the setting of the IO_SMI bit may be lost.
This may happen under a complex set of internal conditions with Intel® Hyper-
Threading Technology enabled and has not been observed with commercially available
software.
Implication:
Due to this erratum, SMI handlers may not be able to identify the occurrence of I/O
SMIs.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU93.
VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are
Different
Problem:
VM entry to 64-bit mode should allow any value for bits [47:0] of the RIP field in the
guest-state area as long as bits 63:48 are identical. Due to this erratum, such a VM
entry may fail if bit 47 of the field has a value different from that of bit 48.
Implication:
It is not possible to perform VM entry to a 64-bit guest that has made a transition to a
non-canonical instruction pointer.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU94.
VM Entry Loading an Unusable SS Might Not Set SS.B to 1
Problem:
If the unusable bit (bit 16) is 1 in the guest SS (Stack Segment) access-rights field, VM
entry should set the B bit (default stack-pointer size) in the SS (stack segment)
register to 1. Due to this erratum, VM entry may instead load SS.B from bit 14 of the
guest SS access-rights field, potentially clearing SS.B to 0.
Implication:
This erratum can affect software only if a far RET instruction is executed after a VM
entry that erroneously clears the B bit and only if the following other three conditions
are also true: (1) the SS register is not loaded between VM entry and far RET; (2) the
far RET instruction is executed in 64-bit mode with an immediate operand; (3) the far
RET instruction makes a transition to compatibility mode without changing CPL
(Current Privilege Level). Due to the far RET being executed with an immediate
operand, an adjustment is made to the stack pointer. Normally, when SS is unusable
the SS.B bit is 1 and the adjustment will be to the 32-bit ESP register. Due to this
erratum, the adjustment will incorrectly be made to the 16-bit SP register. Intel has not
observed this erratum with any commercially available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU95.
FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault
in VMX Non-Root Operation
Problem:
The X87 FSW (FPU Status Word) may be corrupted if execution of a floating-point store
instruction (FST, FSTP, FIST, FISTP, FISTTP) causes a page fault in VMX non-root
operation.
Содержание G6950
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