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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

21

Electrical Specifications

Note:

The LL_ID[1:0] signals are used by the platform to select the correct loadline slope for the processor.

Note:

The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be

used for future processor compatibility or for keying.

2.6

Reserved, Unused, or Test Signals

All Reserved signals must remain unconnected. Connection of these signals to V

CC

, V

TT

,

V

SS

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See

Section 4

for a land listing of the

processor and the location of all Reserved signals.

For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V

SS

). Unused outputs can be left unconnected; however, this may

interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R

TT

). For details see

Table 2-18

.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused
outputs may be terminated on the baseboard or left unconnected. Note that leaving
unused outputs unterminated may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. Signal termination for these signal types
is discussed in the appropriate platform design guidelines.

For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then
terminate the net with a 51

Ω

resistor to V

TT

.

The TESTHI signals must be tied to the processor V

TT

using a matched resistor, where a

matched resistor has a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50

Ω

, then a value

between 40

Ω

and 60

Ω

is required.

Table 2-4.

Loadline Selection Truth Table for LL_ID[1:0]

LL_ID1

LL_ID0

Description

0

0

Reserved

0

1

Dual-Core Intel® Xeon® Processor 5000 Series
Dual-Core Intel® Xeon® Processor 5100 Series

1

0

Reserved

1

1

All Quad-Core Intel® Xeon® Processor 5300 Series

Table 2-5.

Market Segment Selection Truth Table for MS_ID[1:0]

MS_ID1

MS_ID0

Description

0

0

Dual-Core Intel® Xeon® Processor 5000 Series

0

1

Dual-Core Intel® Xeon® Processor 5100 Series

1

0

All Quad-Core Intel® Xeon® Processor 5300 Series

1

1

Reserved

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Содержание E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core Processor

Страница 1: ...Order Number 315569 Revision 001 Quad Core Intel Xeon Processor 5300 Series Datasheet November 2006...

Страница 2: ...nctionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit fun...

Страница 3: ...24 2 10 2 Input Device Hysteresis 25 2 11 Mixing Processors 26 2 12 Absolute Maximum and Minimum Ratings 26 2 13 Processor DC Specifications 27 2 13 1 Flexible Motherboard Guidelines FMB 27 2 13 2 VCC...

Страница 4: ...oop or HALT Snoop State Stop Grant Snoop State 94 7 3 Enhanced Intel SpeedStep Technology 95 8 Boxed Processor Specifications 97 8 1 Introduction 97 8 2 Mechanical Specifications 99 8 2 1 Boxed Proces...

Страница 5: ...ordinates Bottom View 47 6 1 Quad Core Intel Xeon Processor E5300 Series Thermal Profile 81 6 2 Quad Core Intel Xeon Processor X5300 Series Thermal Profiles 82 6 3 Case Temperature TCASE Measurement L...

Страница 6: ...ns 33 2 17 VCC Overshoot Specifications 33 2 18 AGTL Bus Voltage Definitions 35 2 19 FSB Differential BCLK Specifications 35 3 1 Package Loading Specifications 43 3 2 Package Handling Guidelines 44 3...

Страница 7: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 7 Revision History Document Number Revision Description Date 315569 001 Initial Release November 2006...

Страница 8: ...8 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 9: ...logy provides power management capabilities to servers and workstations The Quad Core Intel Xeon Processor 5300 Series features include Advanced Dynamic Execution enhanced floating point and multi med...

Страница 10: ...11 0 will support the power requirements of all frequencies of the processors including Flexible Motherboard Guidelines FMB see Section 2 13 1 Refer to the appropriate platform design guidelines for...

Страница 11: ...A mainstream performance version of the Quad Core Intel Xeon Processor E5300 Series For this document Quad Core Intel Xeon Processor E5300 Series is used to call out specifications that are unique to...

Страница 12: ...d Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Desi...

Страница 13: ...tware Developer s Manual Volume 1 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Intel 64 and IA 32 Archi...

Страница 14: ...Introduction 14 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 15: ...EF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA_MID and GTLREF_DATA_END are used for th...

Страница 16: ...m a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 12 Failure to do so can result...

Страница 17: ...s setting using software see the Intel 64 and IA 32 Architectures Software Developer s Manual This permits operation at lower frequencies than the processor s tested frequency The processor core frequ...

Страница 18: ...ease refer to Table 2 15 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processo...

Страница 19: ...n this table refers to a high voltage level and a 0 refers to a low voltage level The definition provided in Table 2 3 is not related in any way to previous Intel Xeon processors or voltage regulator...

Страница 20: ...2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9...

Страница 21: ...rm design guidelines For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors RTT For details see Table 2 18 TAP Asynchronous GTL inputs and Asy...

Страница 22: ...of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 ADS HIT H...

Страница 23: ...TPCLK CMOS Asynchronous Output Asynchronous BSEL 2 0 VID 6 1 FSB Clock Clock BCLK 1 0 TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Synchronous to TCK TDO Power Other Power Other COMP 3 0 G...

Страница 24: ...be made for TCK TDO TMS and TRST Two copies of each signal may be required with each driving a different voltage level 2 10 Platform Environmental Control Interface PECI DC Specifications PECI is an...

Страница 25: ...able 2 10 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range 0 150 VTT V Vhysteresis Hysteresis 0 1 VTT N A V VN Negative edge threshold voltage 0...

Страница 26: ...thin absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been sub...

Страница 27: ...DC specifications for the PWRGOOD input and TAP signal group are listed in Table 2 15 Table 2 12 through Table 2 16 list the DC specifications for the processor and are valid only while meeting speci...

Страница 28: ...and Figure 2 3 for further details on the average processor current draw over various time durations ICC ICC for Quad Core Intel Xeon Processor E5300 Series core with multiple VID Launch FMB 90 A 4 5...

Страница 29: ...voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for furthe...

Страница 30: ...43 1 2 3 15 VID 0 019 VID 0 034 VID 0 049 1 2 3 20 VID 0 025 VID 0 040 VID 0 055 1 2 3 25 VID 0 031 VID 0 046 VID 0 061 1 2 3 30 VID 0 038 VID 0 053 VID 0 068 1 2 3 35 VID 0 044 VID 0 059 VID 0 074 1...

Страница 31: ...and transient limits Please see Section 2 13 2 for VCC overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 4 for Quad Core Intel Xeon Processor E5300 Serie...

Страница 32: ...high value 4 VIH and VOH may experience excursions above VTT However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Refer to process...

Страница 33: ...n This overshoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC_DIE_SENSE and VSS_DIE...

Страница 34: ...ntegrated into the processor silicon See Table 2 7 for details on which signals do not include on die termination Please refer to Table 2 18 for RTT values Valid high and low levels are determined by...

Страница 35: ...s the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1 4 VHavg is the statistical average of the VH measured by the oscilloscope 5 Overshoot is defined a...

Страница 36: ...crossing point specifications simultaneously 10 VHavg can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes 11 For VIN between 0 V and VH 12 VCROSS is defined as the tota...

Страница 37: ...Signal Group DC specifications for TAP Signal Group AC specifications Figure 2 9 Differential Clock Crosspoint Specification 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840...

Страница 38: ...Electrical Specifications 38 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 39: ...1 socket The package components shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TIM Processor Die Package Substrate Landside capacitors Package Lands...

Страница 40: ...00 Series Datasheet Note Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Desig...

Страница 41: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 41 Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3...

Страница 42: ...Mechanical Specifications 42 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 3 4 Processor Package Drawing Sheet 3 of 3...

Страница 43: ...3 These specifications are based on limited testing for design characterization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is...

Страница 44: ...ling guidelines are for the package only and do not include the limits of the processor socket 3 5 Package Insertion Specifications The Quad Core Intel Xeon Processor 5300 Series can be inserted and r...

Страница 45: ...he top and bottom view of the processor land coordinates respectively The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processor Top side Markings Example...

Страница 46: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM...

Страница 47: ...2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH A...

Страница 48: ...Mechanical Specifications 48 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 49: ...urce Sync Input Output A13 U4 Source Sync Input Output A14 V5 Source Sync Input Output A15 V4 Source Sync Input Output A16 W5 Source Sync Input Output A17 AB6 Source Sync Input Output A18 W6 Source Sy...

Страница 50: ...Output D01 C5 Source Sync Input Output D02 A4 Source Sync Input Output Table 4 1 Land Listing by Land Name Sheet 3 of 22 Pin Name Pin No Signal Buffer Type Direction D03 C6 Source Sync Input Output D0...

Страница 51: ...Output D54 C18 Source Sync Input Output Table 4 1 Land Listing by Land Name Sheet 5 of 22 Pin Name Pin No Signal Buffer Type Direction D55 B16 Source Sync Input Output D56 A17 Source Sync Input Outpu...

Страница 52: ...PROCHOT AL2 ASync GTL Output PWRGOOD N1 Power Other Input REQ0 K4 Source Sync Input Output REQ1 J5 Source Sync Input Output REQ2 M6 Source Sync Input Output REQ3 K6 Source Sync Input Output REQ4 J6 S...

Страница 53: ...ther VCC AC8 Power Other VCC AD23 Power Other VCC AD24 Power Other VCC AD25 Power Other VCC AD26 Power Other Table 4 1 Land Listing by Land Name Sheet 9 of 22 Pin Name Pin No Signal Buffer Type Direct...

Страница 54: ...C AK26 Power Other VCC AK8 Power Other Table 4 1 Land Listing by Land Name Sheet 11 of 22 Pin Name Pin No Signal Buffer Type Direction VCC AK9 Power Other VCC AL11 Power Other VCC AL12 Power Other VCC...

Страница 55: ...VCC M30 Power Other VCC M8 Power Other Table 4 1 Land Listing by Land Name Sheet 13 of 22 Pin Name Pin No Signal Buffer Type Direction VCC N23 Power Other VCC N24 Power Other VCC N25 Power Other VCC...

Страница 56: ...AB1 Power Other VSS AB23 Power Other VSS AB24 Power Other VSS AB25 Power Other Table 4 1 Land Listing by Land Name Sheet 15 of 22 Pin Name Pin No Signal Buffer Type Direction VSS AB26 Power Other VSS...

Страница 57: ...SS AK23 Power Other VSS AK24 Power Other Table 4 1 Land Listing by Land Name Sheet 17 of 22 Pin Name Pin No Signal Buffer Type Direction VSS AK27 Power Other VSS AK28 Power Other VSS AK29 Power Other...

Страница 58: ...VSS F4 Power Other VSS F7 Power Other Table 4 1 Land Listing by Land Name Sheet 19 of 22 Pin Name Pin No Signal Buffer Type Direction VSS H10 Power Other VSS H11 Power Other VSS H12 Power Other VSS H...

Страница 59: ...er VSS V3 Power Other VSS V30 Power Other VSS V6 Power Other VSS V7 Power Other Table 4 1 Land Listing by Land Name Sheet 21 of 22 Pin Name Pin No Signal Buffer Type Direction VSS W4 Power Other VSS W...

Страница 60: ...r Other AA27 VSS Power Other AA28 VSS Power Other AA29 VSS Power Other AA3 VSS Power Other AA30 VSS Power Other AA4 A21 Source Sync Input Output AA5 A23 Source Sync Input Output AA6 VSS Power Other AA...

Страница 61: ...Other AE8 SKTOCC Power Other Output Table 4 2 Land Listing by Land Number Sheet 3 of 20 Pin No Pin Name Signal Buffer Type Direction AE9 VCC Power Other AF1 TDO TAP Output AF10 VSS Power Other AF11 VC...

Страница 62: ...r AH25 VCC Power Other AH26 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 5 of 20 Pin No Pin Name Signal Buffer Type Direction AH27 VCC Power Other AH28 VCC Power Other AH29 VCC Power Ot...

Страница 63: ...ower Other Table 4 2 Land Listing by Land Number Sheet 7 of 20 Pin No Pin Name Signal Buffer Type Direction AL18 VCC Power Other AL19 VCC Power Other AL2 PROCHOT ASync GTL Output AL20 VSS Power Other...

Страница 64: ...No Pin Name Signal Buffer Type Direction B12 D13 Source Sync Input Output B13 RESERVED B14 VSS Power Other B15 D53 Source Sync Input Output B16 D55 Source Sync Input Output B17 VSS Power Other B18 D5...

Страница 65: ...9 VTT Power Other D3 VSS Power Other Table 4 2 Land Listing by Land Number Sheet 11 of 20 Pin No Pin Name Signal Buffer Type Direction D30 VTT Power Other D4 HIT Common Clk Input Output D5 VSS Power O...

Страница 66: ...ut Output G19 DSTBP2 Source Sync Input Output G2 COMP2 Power Other Input G20 DSTBN2 Source Sync Input Output Table 4 2 Land Listing by Land Number Sheet 13 of 20 Pin No Pin Name Signal Buffer Type Dir...

Страница 67: ...r Other K23 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 15 of 20 Pin No Pin Name Signal Buffer Type Direction K24 VCC Power Other K25 VCC Power Other K26 VCC Power Other K27 VCC Power...

Страница 68: ...ut R2 VSS Power Other R23 VSS Power Other Table 4 2 Land Listing by Land Number Sheet 17 of 20 Pin No Pin Name Signal Buffer Type Direction R24 VSS Power Other R25 VSS Power Other R26 VSS Power Other...

Страница 69: ...C Power Other W24 VCC Power Other W25 VCC Power Other W26 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 19 of 20 Pin No Pin Name Signal Buffer Type Direction W27 VCC Power Other W28 VCC...

Страница 70: ...Land Listing 70 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 71: ...ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 37 3 4 lands All bus agents observe the ADS activation to begin parity checking protocol checking address d...

Страница 72: ...tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be b...

Страница 73: ...the system board DBR is used by a debug port interposer so that an in target probe can drive reset If a debug port connector is implemented in the system DBR is a no connect on the Quad Core Intel Xeo...

Страница 74: ...Circuit TCC GTLREF_ADD_MID GTLREF_ADD_END I GTLREF_ADD determines the signal reference level for AGTL address and common clock input lands GTLREF_ADD is used by the AGTL receivers to determine if a si...

Страница 75: ...transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first tran...

Страница 76: ...gent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents 3 RSP I RSP Response Parity is driven by the response agent the agent respo...

Страница 77: ...et Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST I TRST Test Reset r...

Страница 78: ...s two Maximum number of priority agents is one 4 Not all Quad Core Intel Xeon Processor 5300 Series support signals A 37 36 Processors that support these signals will be outlined in the Quad Core Inte...

Страница 79: ...the processor must remain within the minimum and maximum case temperature TCASE specifications as defined by the applicable thermal profile see Table 6 1 and Figure 6 1 for Quad Core Intel Xeon Proces...

Страница 80: ...al profile consists of x P_PROFILE_MIN and y TCASE_MAX P_PROFILE_MIN P_PROFILE_MIN is defined as the processor power at which TCASE calculated from the thermal profile is equal to 50 C Analysis indica...

Страница 81: ...rmal Mechanical Design Guidelines for system and environmental implementation details Figure 6 1 Quad Core Intel Xeon Processor E5300 Series Thermal Profile 40 45 50 55 60 65 70 0 10 20 30 40 50 60 70...

Страница 82: ...ot meet processor Quad Core Intel Xeon Processor X5300 Series Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for det...

Страница 83: ...SE Table 6 4 Quad Core Intel Xeon Processor X5300 Series Thermal Profile A Table Power W TCASE_MAX C P_PROFILE_MIN_A 43 9 50 0 45 50 2 50 51 1 55 51 9 60 52 8 65 53 6 70 54 5 75 55 3 80 56 2 85 57 0 9...

Страница 84: ...d Thermal Monitor TM2 The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications When both are enabled TM2 will be activated first and TM1 will be added if TM...

Страница 85: ...cooling the processor even when the TCC is active continuously Refer to the Quad Core Intel Xeon Processor 5300 Series Thermal Mechanical Design Guidelines for information on designing a thermal solut...

Страница 86: ...ing point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 4 for an illustration of this orde...

Страница 87: ...gned to the processor specifications and cannot be adjusted based on experimental measurements of TCASE or PROCHOT 6 2 6 FORCEPR Signal The FORCEPR force power reduction input can be used by the platf...

Страница 88: ...n the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on Quad Core Intel Xeon Processor 5300 Series i...

Страница 89: ...and targeted response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will p...

Страница 90: ...ty issues due to an abnormal condition on PECI the PECI host controller should take action to protect the system from possible damage It is recommended that the PECI host controller take appropriate a...

Страница 91: ...or 5300 Series support the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the...

Страница 92: ...her Normal Mode or the HALT state See the Intel 64 and IA 32 Intel Architecture Software Developer s Manual Volume III System Programming Guide for more information The system can generate a STPCLK wh...

Страница 93: ...hange the bus to core frequency ratio back to the original value Table 7 2 Extended HALT Maximum Power Symbol Parameter Min Typ Max Unit Notes PEXTENDED_HALT Quad Core Intel Xeon Processor E5300 Serie...

Страница 94: ...Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon ret...

Страница 95: ...within the Normal state as shown in Figure 7 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor b...

Страница 96: ...Features 96 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 97: ...rimarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue The 1U passive 3U active combination solution with th...

Страница 98: ...ed that the CEK spring will ship with the base board and be pre attached prior to shipping Figure 8 2 Boxed Quad Core Intel Xeon Processor 5300 Series 2U Passive Heat Sink Figure 8 3 2U Passive Quad C...

Страница 99: ...ocessor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimensi...

Страница 100: ...Boxed Processor Specifications 100 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 4 Top Side Board Keepout Zones Part 1...

Страница 101: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 101 Boxed Processor Specifications Figure 8 5 Top Side Board Keepout Zones Part 2...

Страница 102: ...Boxed Processor Specifications 102 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 6 Bottom Side Board Keepout Zones...

Страница 103: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 103 Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones...

Страница 104: ...Boxed Processor Specifications 104 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 8 Volumetric Height Keep Ins...

Страница 105: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 105 Boxed Processor Specifications Figure 8 9 4 Pin Fan Cable Connector For Active CEK Heat Sink...

Страница 106: ...Boxed Processor Specifications 106 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink...

Страница 107: ...such that the dynamic loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures...

Страница 108: ...sign considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The pr...

Страница 109: ...sink fan Use of the active configuration in a 2U rackmount chassis is not recommended It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing...

Страница 110: ...or 5300 Series Datasheet The other items listed in Figure 8 3 that are required to compete this solution will be shipped with either the chassis or boards They are as follows CEK Spring supplied by ba...

Страница 111: ...multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Quad Core Intel Xeon Processor 5300 Series based systems designs including...

Страница 112: ...ytic capacitors fall inside of the keepout volume for the LAI In this case it is necessary to move these capacitors to the backside of the board before using the LAI Additionally note that it is possi...

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