INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
40
C30.
Upper Four PAT Entries Not Usable With Mode B or Mode C
Paging
Problem:
The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered
when setting up memory types for the Celeron processor. However, in Mode B or Mode C paging, the upper
four entries do not function correctly for 4-Kbyte pages. Specifically, bit seven of page table entries that
translate addresses to 4-Kbyte pages should be used as the upper bit of a three-bit index to determine the
PAT entry that specifies the memory type for the page. When Mode B (CR4.PSE = 1) and/or Mode C
(CR4.PAE) are enabled, the processor forces this bit to zero when determining the memory type regardless of
the value in the page table entry. The upper four entries of the PAT function correctly for 2-Mbyte and 4-Mbyte
large pages (specified by bit 12 of the page directory entry for those translations).
Implication:
Only the lower four PAT entries are useful for 4-Kbyte translations when Mode B or C paging is
used. In Mode A paging (4-Kbyte pages only), all eight entries may be used. All eight entries may be used for
large pages in Mode B or C paging.
Workaround:
None identified
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
C31.
Incorrect Memory Type May Be Used When MTRRs Are
Disabled
Problem:
If the Memory Type Range Registers (MTRRs) are disabled without setting the CR0.CD bit to
disable caching, and the Page Attribute Table (PAT) entries are left in their default setting, which includes
UC- memory type (PCD = 1, PWT = 0; see the
Intel Architecture Software Developer’s Manual, Volume 3:
System Programming Guide,
for details), data for entries set to UC- will be cached as if the memory type were
writeback (WB). Also, if the page tables are set to a memory type other than UC-, then the effective memory
type used will be that specified by the page tables and PAT. Any regions of memory normally forced to UC by
the MTRRs (such as the VGA video region) may now be incorrectly cached and speculatively accessed.
Even if the CR0.CD bit is correctly set when the MTRRs are disabled and the PAT is left in its default state,
then retries and out of order retirement of UC accesses may occur, contrary to the strong ordering expected
for these transactions.
Implication:
The occurrence of this erratum may result in the use of incorrect data and unpredictable
processor behavior when running with the MTRRs disabled. Interaction between the mouse, cursor, and VGA
video display leading to video corruption may occur as a symptom of this erratum as well.
Workaround:
Ensure that when the MTRRs are disabled, the CR0.CD bit is set to disable caching. This
recommendation is described in
Intel Architecture Software Developer’s Manual, Volume 3: System
Programming Guide
. If it is necessary to disable the MTRRs, first clear the PAT register before setting the
CR0.CD bit, flushing the caches, and disabling the MTRRs to ensure that UC memory type is always returned
and strong ordering is maintained.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
