INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
4
IDENTIFICATION INFORMATION
Complete identification information of the Celeron processor can be found in the
Intel Processor Identification
and the CPUID Instruction
application note (Document Number 241618).
The Celeron processor can be identified by the following values:
Family
1
Model
2
Brand
ID
3
0110
0101
00h = Not Supported
0110
0110
00h = Not Supported
0110
1000
01h = “Intel
®
Celeron
®
Processor”
0110 1011
4
03h = “Intel
®
Celeron
®
Processor”
NOTES:
1.
The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID
instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible
through Boundary Scan.
2.
The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID
instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through
Boundary Scan.
3.
The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a 1 in the EAX
register.
4.
This only applies to units with processor signature of 0x6B1.
The Celeron processor’s second level (L2) cache size can be determined by the following register contents:
0-Kbyte Unified L2 Cache
1
40h
128-Kbyte Unified L2 Cache
1
41h
256-Kbyte 8 way set associative 32byte line
size, L2 Cache
1
82h
NOTE:
1.
When the EAX register contains a value of 2, the CPUID instruction loads the EAX, EBX, ECX and EDX registers with
descriptors that indicate the processors cache and TLB characteristics. The lower 8 bits of the EAX register (AL) contain
a value that identifies the number of times the CPUID has to be executed to obtain a complete image of the processor’s
caching systems. The remainder of the EAX register, the EBX, ECX and EDX registers contain the cache and TLB
descriptors. When bit 31 in a given register is zero, that register contains valid 8-bit descriptors. To decode descriptors,
move sequentially from the most significant byte of the register down through the least significant byte of the register.
Assuming bit 31 is 0, then that register contains valid cache or TLB descriptors in bits 24 through 31, bits 16 through 23,
bits 8 through 15 and bits 0 through 7. Software must compare the value contained in each of the descriptor bit fields
according to the definition of the CPUID instruction . For more details refer to the
AP-485 Intel Processor Identification
and the CPUID Instruction Application Note
.
