42
Specification Update
AAO74.
Concurrent Updates to a Segment Descriptor May be Lost
Problem:
If a logical processor attempts to set the accessed bit in a code or data segment
descriptor while another logical processor is modifying the same descriptor, both
modifications of the descriptor may be lost.
Implication:
Due to this erratum, updates to segment descriptors may not be preserved. Intel has
not observed this erratum with any commercially available software or system.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO75.
PMIs May be Lost During Core C6 Transitions
Problem:
If a performance monitoring counter overflows and causes a PMI (Performance
Monitoring Interrupt) at the same time that the core is entering C6, then the PMI may
be lost.
Implication:
PMIs may be lost during a C6 transition.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO76.
Uncacheable Access to a Monitored Address Range May Prevent
Future Triggering of the Monitor Hardware
Problem:
It is possible that an address range which is being monitored via the MONITOR
instruction could be written without triggering the monitor hardware. A read from the
monitored address range which is issued as uncacheable (for example having the
CR0.CD bit set) may prevent subsequent writes from triggering the monitor hardware.
A write to the monitored address range which is issued as uncacheable, may not trigger
the monitor hardware and may prevent subsequent writes from triggering the monitor
hardware.
Implication:
The MWAIT instruction will not exit the optimized power state and resume program flow
if the monitor hardware is not triggered.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO77.
BIST Results May be Additionally Reported After a GETSEC[WAKEUP]
or INIT-SIPI Sequence
Problem:
BIST results should only be reported in EAX the first time a logical processor wakes up
from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally
reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep
state using the GETSEC[WAKEUP] command.
Implication:
An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero
value is expected. RLP's waking up for the SENTER sleep state using the
GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than
before going into the SENTER sleep state.
Workaround:
If necessary software may save the value in EAX prior to launching into the secure
environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence.
Status:
For the steppings affected, see the Summary Tables of Changes.
Содержание BV80605001914AG - Processor - 1 x Xeon X3430
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