Intel B5120, Руководство по обслуживанию

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Schematic Diagrams
B - 24 PCH 3/9 (DMI, FDI, MISC)
B.Schematic Diagrams
PCH 3/9 (DMI, FDI, MISC)
S US _P WR _A CK
P M_CL KR UN #
D02
SY S _R ES ET#
SW I#
RS MR S T#
PM_C LK RU N#
AU XP PW R OK _R
PC IE_ W AK E#
PM_MP WR OK
SU SB #
P M_BA TLOW #
SU S _PW R _A CK
S B_PW R OK
D MI_ CO MP_R
PM_S LP _L AN #
S4_ STATE#
PC IE _W AK E#
FD I_L SY NC 1_R
A C_PR ES EN T
PM_B ATLO W #
AC _P R ES EN T
PW R _B TN #
P M_ MP W ROK
FD I_I NT_R
FD I_F SY NC 0 _R
FD I_F SY NC 1 _R
FD I_L SY NC 0_R
U 20C
7 4L VC 08P W
9
1 0
8
14
7
R 47 6 8 .2K _0 4
R253 10K _0 4
AL L_SY S_PW RGD
R 231
10 K_ 04
R 229 *10m il_short
R 24 3 1 0K _04
R272 10K_04
U 20D
7 4LV C08P W
1 2
1 3
1 1
14
7
R N4 4
1K_8P 4R _04
8 1
7 2
6
5
3
4
R 24 5 * 10 K_0 4
R508 49.9_ 1% _04
R7 22 1K_ 04
R 45 8 1 0K _04
DM
I
FD
I
Sys
t
em P
owe
r M
ana
ge
ment
U 30C
Ibex Pea k- M_Rev 0_ 9
D MI0R XN
BC 24
D MI1R XN
BJ 22
D MI2R XN
A W 20
D MI3R XN
BJ 20
D MI0R XP
BD 24
D MI1R XP
BG22
D MI2R XP
BA 20
D MI3R XP
BG20
D MI0TXN
BE 22
D MI1TXN
BF 21
D MI2TXN
BD 20
D MI3TXN
BE 18
D MI0TXP
BD 22
D MI1TXP
BH 21
D MI2TXP
BC 20
D MI3TXP
BD 18
D MI_Z CO MP
BH 25
D MI_I RC OMP
BF 25
FD I_RXN0
BA 18
FD I_RXN1
BH 17
FD I_RXN2
BD 16
FD I_RXN3
BJ 16
FD I_RXN4
BA 16
FD I_RXN5
BE 14
FD I_RXN6
BA 14
FD I_RXN7
BC 12
F DI_ RXP0
BB 18
F DI_ RXP1
BF 17
F DI_ RXP2
BC 16
F DI_ RXP3
BG16
F DI_ RXP4
AW 16
F DI_ RXP5
BD 14
F DI_ RXP6
BB 14
F DI_ RXP7
BD 12
FD I_ FS Y N C0
BF 13
FD I_ FS Y N C1
BH 13
FD I_LS Y N C0
BJ 12
FD I_LS Y N C1
BG14
FD I_INT
BJ 14
PMSY N CH
BJ 10
TP 23
N2
SLP_M#
K8
SLP _S 3#
P12
SLP _S 4#
H7
S LP_ S5 # / GPIO63
E4
SY S_R E SE T#
T6
SY S_P W RO K
M6
PW RBTN #
P5
R I#
F 14
W AK E#
J1 2
SU S_STAT# / GPIO61
P8
S US CLK / GPIO62
F3
AC PR ES EN T / GP IO 31
P7
LAN _R ST#
A 10
ME PW RO K
K5
BATLOW # / GP IO 72
A6
PW ROK
B 17
CL KR UN # / GPIO32
Y 1
SU S_P W R_ AC K / G PIO30
M1
R S MR ST#
C 16
D R AMPW R OK
D 9
SLP_LA N#
F6
U20B
74 LV C0 8PW
4
5
6
14
7
R 26 7 1 K_ 04
R 25 0 * 10 K_0 4
R819
10K_04
U2 0A
74 LVC 08PW
1
2
3
14
7
R 27 1 1 0K _04
R 239 *10m il_short
R495 10K_04
R 226 2K _0 4
R 228
1K_04
R 46 4 8 .2K _0 4
R 227 *10m il_short
3. 3V
3.3V
1. 1VS _V TT
DMI_R XN 0 3
3.3 VS
3.3 V
3 .3 VS
3.3 V
3 .3V
DMI_R XP 1 3
DMI_R XP 0 3
DMI_R XN 3 3
DMI_R XN 2 3
DMI_R XN 1 3
DMI_ TXN 2 3
DMI_ TXN 1 3
DMI_ TXN 0 3
DMI_R XP 3 3
DMI_R XP 2 3
RS MR ST# 3 7
DMI_ TXP 3 3
DMI_ TXP 2 3
DMI_ TXP 1 3
DMI_ TXP 0 3
DMI_ TXN 3 3
H_PM_S Y N C 4
S W I# 3 7
AC _P R ES EN T 25, 37
S US _P W R_ AC K 37
PM_D RA M_ PW RGD 4
3.3V S 2 ,10 ,11,12,13,1 4,2 1,2 2,25, 26, 27 ,28,30,31,32,3 3,3 4,36,37, 38, 44, 45,47
3.3V 3 ,4, 12, 13, 21,22 ,25 ,26 ,28,30,31,3 2,3 3, 34, 35, 38 ,40 ,41,42,43
1.1V S_VTT 2,4,6, 7,20,2 1,2 2,2 6, 27, 28 ,42 ,44
PW R_ BTN# 3 7
PC IE_ W AKE# 30,33
SU SC # 37,41
SU SB # 30,37,4 0
1.1 VS _V TT_PW R GD 4,4 2
1. 1VS_V TT_E N 42
H_ VTTPW R GD 4
D ELAY _P W RG D 4 ,44
S Y S _P W ROK
EXT-LAN
IBEXPEAK - M (DMI,FDI,GPIO)
D D R1.5V _P WR GD 41
PM_C LK RU N # 31
S4 _S TA TE# 3 1
A LL _S Y S _P WR GD 12 ,37
? ? SU SB# - ->? ? 1 .1 VS_ VT T? SU SP EN D? ? ? ? ?
Auburndale Graphics Disable Guideline
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0]
can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left
floating on the Auburndale
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1],
FDI_LSYNC[0], FDI_LSYNC[1], and
FDI_INT signals should be tied to GND (through
1K ? % resistors) in the common
motherboard design case. Please not that if
these signals are left floating, there are no
functional impacts but a small amount of power
(~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on Auburndale can be left as
no connect.
FOR RESET SWITCH (? ? ? )
SU SB #
SY S _PW R OK
SB _P W ROK
PW R _B TN #
SW I#
AL L_ SY S_PW RGD
PM_S LP_ LA N#
Sheet 23 of 56
PCH 3/9
(DMI, FDI, MISC)