Intel B5120, Руководство по обслуживанию

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Schematic Diagrams
CPU 2/7 (CLK, MISC) B - 5
B.Sch
e
m
a
tic D
iag
rams
CPU 2/7 (CLK, MISC)
R16 9 *1.5 K_1%_04
SM_D RA MR ST#
IN 3.3 V
1.5VS_CP U 7,38
? ? I BEX CO NTR OL
H_PR OC HOT# 44
H_CPU RS T#
Q3 6
*R JU0 03N 03T10 6
G
D S
DDR3 Compensation Signals
XD P_TDO _R
H_P ROCH OT#_D
Processor Pullups
XD P_TDI_M
XD P_TRS T#
U 40
* MC 74V HC 1G0 8D FT1 G
1
2
5
4
3
R 155 0_04
1.5V 9 ,10,11,20, 38, 41
3.3V
If PR OCH OT# is n ot use d, the n i t m ust be te rmi nat ed
wi th a 5 0-O pu ll -up re sis tor to VT T_1 .1 rai l.
PROCESSOR 2/7 ( CLK,MISC,JTAG )
H_COMP2
H_COMP3
H_COMP1
H_COMP0
R 83 *68_0 4
R 115 *1 2.4 K_1%_04
R 81 *5 1_04
R 76 *5 1_04
R 114 10K_04
R14 7 1 .5K _1%_04
R 102 49 .9_1%_ 04
R 91 20 _1%_04
R88 0_0 4
R 141
1 .1K _1%_04
R 123 *0 _04
R 429 24 .9_1 %_04
R 87 49 .9_1%_ 04
R 79 51_0 4
R 80 *5 1_04
R 122 10K_04
C
LOC
KS
M
ISC
T
HER
MAL
P
WR
M
ANA
GEM
EN
T
DD
R3
MIS
C
JTA
G &
B
PM
U 28B
G989 PIN U PGA
S M_ RC OMP[1]
A M1
S M_ RC OMP[2]
A N1
SM_D RAMR ST#
F 6
S M_ RC OMP[0]
A L1
BC LK#
B 16
BC LK
A 16
B CLK_I TP#
A T30
BC LK_ITP
A R30
P EG_C LK#
D 16
PEG_C LK
E 16
DPLL_ REF_S SC LK#
A 17
D PLL _RE F_SSC LK
A 18
CATER R#
A K14
CO MP3
A T23
PEC I
A T15
PROCH OT#
A N26
THERMTR IP#
A K15
RES ET_OB S#
A P26
VCC PW RG OO D_1
A N14
VCC PW RG OO D_0
A N27
SM_DR AMPW RO K
A K13
VTTPW RGOOD
A M15
RSTIN#
A L14
PM_E XT_ TS#[0]
A N15
PM_E XT_ TS#[1]
A P1 5
P RD Y #
A T28
PRE Q#
A P2 7
TCK
A N28
TMS
A P2 8
TR ST#
A T27
TDI
A T29
TDO
A R27
TD I_M
A R29
TDO_M
A P2 9
DB R#
A N25
B PM#[0]
A J22
B PM#[1]
A K2 2
B PM#[2]
A K2 4
B PM#[3]
A J24
B PM#[4]
A J25
B PM#[5]
A H22
B PM#[6]
A K2 3
B PM#[7]
A H23
CO MP2
A T24
PM_SY NC
A L15
TAP PW RGOO D
A M26
CO MP1
G16
CO MP0
A T26
SKTOC C#
A H24
R 86 68 _04
R 95 20 _1%_04
R 137
3 K_ 1%_04
R10 7 * 0_0 4
R 118 *0 _04
TRACE WIDTH 10MIL, LENGTH <500MILS
R 431 10 0_1%_04
R 146
750_1%_04
R 418 49 .9_1%_ 04
R 84 51_0 4
R 82 *5 1_04
R 428 13 0_1%_04
XD P_TMS
1 .1V S_V TT
1 .1V S_V TT
1. 5VS _C PU
1 .1VS _V TT
BCLK_CPU _P 26
H _CP UP WR GD 26
BU F_ PLT_R ST# 2 5,30,33,37
PM_D RA M_PW RGD 23
H _VTTP WR GD 23
BCLK_CPU _N 26
H _THR MTR IP# 26
CLK_E XP_N 2 2
CLK_E XP_P 22
H _P EC I 2 6,37
1.1VS_VTT 2,6,7,20 ,21, 22, 23,2 6,27,28,42 ,44
PM_E XTTS#_ EC 3
TS #_D IMM0_ 1 1 0,11
DELAY _P WR GD 23 ,44
H _P M_SY N C 23
Intel change
4.75K -->1.1K
D RA MR ST_CTR L 9,26
DRA MP WR GD _C PU
D DR 3_D RA MR ST# 1 0,11
PM_EXTTS#[0 ]
R10 3 *10mil_ short
H_PROCH OT#_D
R14 0 *10mil_ short
3.3V 3 ,12,13,21, 22, 23,25,26,2 8,30,31,32 ,33, 34, 35,3 8,40,41,42 ,43
R 85 *5 1_04 XD P_TDO _R
R 148 * 10m il_sho rt
XD P_TDO _M
H_C PU RS T#
Processor Compensation
Signals
H_P WR GD _XD P
PLT_RS T#_R
XD P_P RE Q#
XD P_TCL K
XD P_TRS T#
XD P_TMS
Co nne ct to the Pr oce sso r ( VTT PWR GOO D) VTT _1. 1 VR pow er
go od sig nal to pr oce sso r. Sig nal vo lta ge lev el is 1. 1 V .
R 180 * 8.2 K_0 4
R 153
*100K _04
H_C OMP3
SY S_A GEN T_PW RO K
H_C OMP2
PM_EXTTS#[1 ]
1.1V S_V TT_PW RGD 23, 42
H_C OMP1
Sig nal f rom PC H t o P roc ess or
Con nec t to PCH (P LT_ RST #)
(ne eds t o b e l eve l t ran sla ted
fro m 3 .3 V to 1.1 V) .
SM_D RAMRS T#
SM_R COMP_0
XD P_TDO _M
XD P_TDI_R
SM_R COMP_1
R 144
* 1K_04
1 .5V
VDD PW RGOOD_ R
SM_R COMP_2
H_C ATERR #
XD P_P RE Q#
XD P_TCLK
XD P_TDI_R
C 707
*47n_50V _0 4
H_C OMP0
XD P_TDI_M
B SS1 38 ( V GS 1.5 V )
XD P_TDO _M
SM_R CO MP_2
SM_R CO MP_1
SM_R CO MP_0
VD DP WR GOOD _R
H_CATER R#
Sheet 4 of 56
CPU 2/7
(CLK, MISC)