Intel 848P, Руководство по тепловому проектированию

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Product Specifications
R
10 Intel
®
848P Chipset Thermal Design Guide
2.2 Thermal Specifications
To ensure proper operation and reliability of the MCH, the temperature must be at or below the
maximum value specified in Table 1. System and component level thermal enhancements are
required to dissipate the heat generated and maintain the MCH within specifications. Chapter 3
provides the thermal metrology guidelines for case temperature measurements. The MCH should
also operate above the minimum case temperature specification listed in Table 1.
Table 1. Intel
®
82848P MCH Case Temperature Specifications
Parameter Value Notes
T
C-MAX
99°C 1
T
C-MIN
0 °C 1
NOTES:
1. Thermal specifications assume an attached heatsink is present.
2.3 Thermal Design Power (TDP)
Thermal design power (TDP) is the estimated power dissipation of the MCH based on normal
operating conditions including V
CC
and T
C-MAX
while executing real worst-case power intensive
applications. This value is based on expected worst-case data traffic patterns and usage of the chipset
and does not represent a specific software application. TDP attempts to account for expected
increases in power due to variation in chipset current consumption due to silicon process variation,
processor speed, DRAM capacitive bus loading, and temperature. However, since these variations
are subject to change, the TDP cannot guarantee that all applications will not exceed the TDP value.
The system designer must design a thermal solution for the MCH such that it maintains T
C
below T
C-
MAX
for a sustained power level equal to TDP. The TDP value can be used for thermal design if the
chipset thermal protection mechanisms are enabled. Intel chipsets provide a hardware-based fail-safe
mechanism incorporated to keep the product temperature in specification in the event of unusually
strenuous usage above the TDP power.
The MCH provides a hardware-based mechanism to reduce MCH power by limiting the traffic that
occurs to certain interfaces. Traffic limits are programmed into the chipset registers during system
boot as part of the Intel supplied BIOS reference code.