82543GC Gigabit Ethernet Controller Specification Update
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Implication
:
Corrupted descriptor writebacks may include writing back unconsumed descriptors, descriptor writebacks to
incorrect addresses, or writebacks missed altogether. In addition, the device may cease to access the PCI bus
or cease packet transmission. If the device hangs, a full software or hardware reset is needed.
Workaround
:
Leave WTHRESH at its default value of 0. Descriptors will be written back immediately.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
36. Bus Initialization with Some Chipsets
Problem:
Upon initialization, the 82543GC controller samples the REQ64# signal on the rising (inactive) edge of RST#. If
REQ64# is sampled low (asserted), the controller starts up with a 64-bit bus width.
The PCI Local Bus Specification calls for 0 ns. minimum input hold time on this signal. However, the 82543GC
controller requires 1 ns. input hold time.
Implication:
If the signal does not have sufficient hold time, the 82543GC controller could power up with incorrect bus width
(64 versus 32 bits).
Many bridges and chipsets drive the REQ64# signal with a full clock of hold time past the rising edge of RST#
and this problem will not be encountered. Other loads on the PCI bus may affect the severity of the problem.
Workaround:
For embedded designs, verify that the system bridge will deliver a full clock of hold time. If the problem is
encountered on an add-in board, try moving the board to a connector on another bus segment.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82545EM/82546EB Gigabit Ethernet
Controllers.
37. Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups
Problem:
The 82543GC Controller Receive Delay Timer Ring Register (RDTR) is used to delay interrupt notification until
a number of microseconds elapse past the last receive packet in a sequence of packets. Under high traffic
conditions, this function can occasionally lead to lockups of both receive and transmit. The lockups are due to a
request queue problem in the DMA control logic.
Implication:
If lockup occurs, either a hardware or software reset will be required. Ethernet performance under some OSes
(e.g., Linux) will be reduced if the feature is disabled.
Workaround:
Do not use the receive delay timer ring. Leave RDTR at its 0x00000000 default. Other techniques can be used
to moderate receive interrupts: not using descriptor writebacks, or querying the receive descriptor head pointer
(approximate indication of descriptors used).
Intel’s Linux driver continues to use RDTR, but documentation warns to turn it off if problems are seen. Other
Intel drivers did not previously use the feature.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
38. Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000
Problem
:
If the controller calculates a transmit TCP checksum as 0x0000, it will automatically change the checksum to
0xFFFF.
Specifications call for 0xFFFF be substituted for 0x0000 for UDP packets to distinguish UDP packets that carry
no checksum. However, the modification does not apply to TCP packets.
Implication
:
If the receiving station is running MS-DOS and calculates a receive checksum of 0x0000, it will flag an error if
the checksum contained in the packet is 0xFFFF. Other operating systems treat 0x0000 and 0xFFFF as
equivalent in one’s complement math. UDP checksums are correct.
Workaround
:
Intel modified the DOS Ethernet driver to check for a received checksum of 0xFFFF on a TCP/IP packet and
change it back to 0x0000 before passing the packet to the operating system.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
